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LR is a 32-bit int reg
llvm-svn: 15273
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@ -79,11 +79,11 @@ def GPRC :
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RegisterClass<i32, 4,
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[R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
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R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
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R16, R15, R14, R13, R0, R1]>
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R16, R15, R14, R13, R0, R1, LR]>
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{
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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return end()-2;
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return end()-3;
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}
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}];
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}
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