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https://github.com/RPCS3/llvm-mirror.git
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AMDGPU/GlobalISel: Select G_UNMERGE_VALUES
llvm-svn: 365483
This commit is contained in:
Matt Arsenault
parent
aef2f43c67
commit
70204398c8
@ -363,6 +363,50 @@ bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) const {
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return true;
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}
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bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
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MachineBasicBlock *BB = MI.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const int NumDst = MI.getNumOperands() - 1;
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MachineOperand &Src = MI.getOperand(NumDst);
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Register SrcReg = Src.getReg();
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Register DstReg0 = MI.getOperand(0).getReg();
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LLT DstTy = MRI.getType(DstReg0);
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LLT SrcTy = MRI.getType(SrcReg);
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const unsigned DstSize = DstTy.getSizeInBits();
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const unsigned SrcSize = SrcTy.getSizeInBits();
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const DebugLoc &DL = MI.getDebugLoc();
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const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, TRI);
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const TargetRegisterClass *SrcRC =
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TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank, MRI);
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if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI))
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return false;
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const unsigned SrcFlags = getUndefRegState(Src.isUndef());
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// Note we could have mixed SGPR and VGPR destination banks for an SGPR
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// source, and this relies on the fact that the same subregister indices are
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// used for both.
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ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);
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for (int I = 0, E = NumDst; I != E; ++I) {
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MachineOperand &Dst = MI.getOperand(I);
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BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
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.addReg(SrcReg, SrcFlags, SubRegs[I]);
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const TargetRegisterClass *DstRC =
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TRI.getConstrainedRegClassForOperand(Dst, MRI);
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if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, MRI))
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return false;
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}
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MI.eraseFromParent();
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return true;
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}
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bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
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return selectG_ADD(I);
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}
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@ -1185,6 +1229,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
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case TargetOpcode::G_MERGE_VALUES:
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case TargetOpcode::G_CONCAT_VECTORS:
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return selectG_MERGE_VALUES(I);
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case TargetOpcode::G_UNMERGE_VALUES:
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return selectG_UNMERGE_VALUES(I);
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case TargetOpcode::G_GEP:
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return selectG_GEP(I);
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case TargetOpcode::G_IMPLICIT_DEF:
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@ -76,6 +76,7 @@ private:
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bool selectG_ADD(MachineInstr &I) const;
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bool selectG_EXTRACT(MachineInstr &I) const;
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bool selectG_MERGE_VALUES(MachineInstr &I) const;
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bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
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bool selectG_GEP(MachineInstr &I) const;
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bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
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bool selectG_INSERT(MachineInstr &I) const;
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231
test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
Normal file
231
test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
Normal file
@ -0,0 +1,231 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s 2> %t | FileCheck -check-prefix=GCN %s
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# RUN: FileCheck -check-prefix=ERR %s < %t
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# ERR-NOT: remark:
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# ERR: remark: <unknown>:0:0: cannot select: %1:sgpr(s64), %2:sgpr(s64), %3:sgpr(s64) = G_UNMERGE_VALUES %0:sgpr(s192) (in function: test_unmerge_values_s_s64_s_s64_s64_s_s192)
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# ERR-NOT: remark:
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---
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name: test_unmerge_values_v_s32_v_s32_v_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: test_unmerge_values_v_s32_v_s32_v_s64
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
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; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: test_unmerge_values_s_s32_s_s32_s_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s_s64
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
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; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: test_unmerge_values_v_s32_s_s32_s_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: test_unmerge_values_v_s32_s_s32_s_s64
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
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; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: test_unmerge_values_s_s32_v_s32_s_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
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; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY undef %2.sub0:sreg_64_xexec
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY undef %2.sub1:sreg_64_xexec
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; GCN: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]]
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%1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES undef %0:sgpr(s64)
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: test_unmerge_values_s_s32_s_s32_s32_s_s96
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2
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; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s96
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; GCN: liveins: $sgpr0_sgpr1_sgpr2
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; GCN: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
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; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub2
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; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]]
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%0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
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%1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2, implicit %3
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...
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---
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name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128
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; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub2
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; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub3
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; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]]
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%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32), %4:sgpr(s32) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2, implicit %3, implicit %4
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...
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---
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name: test_unmerge_values_s_s64_s_s64_s_s128
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN-LABEL: name: test_unmerge_values_s_s64_s_s64_s_s128
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; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]].sub0_sub1
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; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]].sub2_sub3
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; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
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%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:sgpr(s64), %2:sgpr(s64) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: test_unmerge_values_s_s64_s_s64_s64_s_s192
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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%0:sgpr(s192) = G_IMPLICIT_DEF
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%1:sgpr(s64), %2:sgpr(s64), %3:sgpr(s64) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2, implicit %3
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...
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---
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name: test_unmerge_values_rc_set_def_v_s32_v_s32_v_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: test_unmerge_values_rc_set_def_v_s32_v_s32_v_s64
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
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; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr_32(s32), %2:vgpr_32(s32) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: test_unmerge_values_rc_set_use_v_s32_v_s32_v_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: test_unmerge_values_rc_set_use_v_s32_v_s32_v_s64
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
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; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
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%0:vreg_64(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
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S_ENDPGM 0, implicit %1, implicit %2
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...
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