mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 19:12:56 +02:00
[mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions
Differential Revision: http://reviews.llvm.org/D13929 llvm-svn: 251098
This commit is contained in:
Zlatko Buljan
parent
c16a88d64c
commit
703131e673
@ -28,19 +28,6 @@ class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
|
||||
let Inst{10-0} = op;
|
||||
}
|
||||
|
||||
class POOL32A_AC2R_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
|
||||
bits<2> ac;
|
||||
bits<5> rs;
|
||||
bits<5> rt;
|
||||
|
||||
let Inst{31-26} = 0;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = rs;
|
||||
let Inst{15-14} = ac;
|
||||
let Inst{13-6} = funct;
|
||||
let Inst{5-0} = 0b111100;
|
||||
}
|
||||
|
||||
class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
|
||||
bits<5> rt;
|
||||
bits<5> rs;
|
||||
@ -77,3 +64,41 @@ class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
|
||||
let Inst{10} = 0b0;
|
||||
let Inst{9-0} = op;
|
||||
}
|
||||
|
||||
class POOL32A_2RSA4_FMT<string opstr, bits<12> op> : MMDSPInst<opstr> {
|
||||
bits<5> rt;
|
||||
bits<5> rs;
|
||||
bits<4> sa;
|
||||
|
||||
let Inst{31-26} = 0b000000;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = rs;
|
||||
let Inst{15-12} = sa;
|
||||
let Inst{11-0} = op;
|
||||
}
|
||||
|
||||
class POOL32A_2RSA3_FMT<string opstr, bits<7> op> : MMDSPInst<opstr> {
|
||||
bits<5> rt;
|
||||
bits<5> rs;
|
||||
bits<3> sa;
|
||||
|
||||
let Inst{31-26} = 0b000000;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = rs;
|
||||
let Inst{15-13} = sa;
|
||||
let Inst{12-6} = op;
|
||||
let Inst{5-0} = 0b111100;
|
||||
}
|
||||
|
||||
class POOL32A_2RSA5B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
|
||||
bits<5> rt;
|
||||
bits<5> rs;
|
||||
bits<5> sa;
|
||||
|
||||
let Inst{31-26} = 0b000000;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = rs;
|
||||
let Inst{15-11} = sa;
|
||||
let Inst{10} = 0b0;
|
||||
let Inst{9-0} = op;
|
||||
}
|
||||
|
||||
@ -27,14 +27,14 @@ class ADDUH_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh.qb", 0b00101001101>;
|
||||
class ADDUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh_r.qb", 0b10101001101>;
|
||||
class ADDSC_MM_ENC : POOL32A_3RB0_FMT<"addsc", 0b1110000101>;
|
||||
class ADDWC_MM_ENC : POOL32A_3RB0_FMT<"addwc", 0b1111000101>;
|
||||
class DPA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpa.w.ph", 0b00000010>;
|
||||
class DPAQ_S_W_PH_MM_ENC : POOL32A_AC2R_FMT<"dpaq_s.w.ph", 0b00001010>;
|
||||
class DPAQ_SA_L_W_MM_ENC : POOL32A_AC2R_FMT<"dpaq_sa.l.w", 0b01001010>;
|
||||
class DPAQX_S_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_s.w.ph", 0b10001010>;
|
||||
class DPAQX_SA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_sa.w.ph", 0b11001010>;
|
||||
class DPAU_H_QBL_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbl", 0b10000010>;
|
||||
class DPAU_H_QBR_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbr", 0b11000010>;
|
||||
class DPAX_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpax.w.ph", 0b01000010>;
|
||||
class DPA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpa.w.ph", 0b00000010>;
|
||||
class DPAQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"dpaq_s.w.ph", 0b00001010>;
|
||||
class DPAQ_SA_L_W_MM_ENC : POOL32A_2RAC_FMT<"dpaq_sa.l.w", 0b01001010>;
|
||||
class DPAQX_S_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpaqx_s.w.ph", 0b10001010>;
|
||||
class DPAQX_SA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpaqx_sa.w.ph", 0b11001010>;
|
||||
class DPAU_H_QBL_MM_ENC : POOL32A_2RAC_FMT<"dpau.h.qbl", 0b10000010>;
|
||||
class DPAU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpau.h.qbr", 0b11000010>;
|
||||
class DPAX_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpax.w.ph", 0b01000010>;
|
||||
class ABSQ_S_PH_MM_ENC : POOL32A_2R_FMT<"absq_s.ph", 0b0001000100>;
|
||||
class ABSQ_S_W_MM_ENC : POOL32A_2R_FMT<"absq_s.w", 0b0010000100>;
|
||||
class ABSQ_S_QB_MMR2_ENC : POOL32A_2R_FMT<"absq_s.qb", 0b0000000100>;
|
||||
@ -45,8 +45,18 @@ class MSUB_DSP_MM_ENC : POOL32A_2RAC_FMT<"msub", 0b10101010>;
|
||||
class MSUBU_DSP_MM_ENC : POOL32A_2RAC_FMT<"msubu", 0b11101010>;
|
||||
class MULT_DSP_MM_ENC : POOL32A_2RAC_FMT<"mult", 0b00110010>;
|
||||
class MULTU_DSP_MM_ENC : POOL32A_2RAC_FMT<"multu", 0b01110010>;
|
||||
class SHLL_PH_MM_ENC : POOL32A_2RSA4_FMT<"shll.ph", 0b001110110101>;
|
||||
class SHLL_S_PH_MM_ENC : POOL32A_2RSA4_FMT<"shll_s.ph", 0b101110110101>;
|
||||
class SHLL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shll.qb", 0b0100001>;
|
||||
class SHLLV_PH_MM_ENC : POOL32A_3R_FMT<"shllv.ph", 0b00000001110>;
|
||||
class SHLLV_S_PH_MM_ENC : POOL32A_3R_FMT<"shllv_s.ph", 0b10000001110>;
|
||||
class SHLLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shllv.qb", 0b1110010101>;
|
||||
class SHLLV_S_W_MM_ENC : POOL32A_3RB0_FMT<"shllv_s.w", 0b1111010101>;
|
||||
class SHLL_S_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shll_s.w", 0b1111110101>;
|
||||
class SHRA_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra.qb", 0b0000111>;
|
||||
class SHRA_R_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra_r.qb", 0b1000111>;
|
||||
|
||||
// Instruction defs.
|
||||
// Instruction desc.
|
||||
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
|
||||
InstrItinClass itin, RegisterOperand ROD,
|
||||
RegisterOperand ROS = ROD> {
|
||||
@ -63,6 +73,52 @@ class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
|
||||
class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
|
||||
"absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
|
||||
|
||||
class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
SDPatternOperator ImmPat, InstrItinClass itin,
|
||||
RegisterOperand RO, Operand ImmOpnd> {
|
||||
dag OutOperandList = (outs RO:$rt);
|
||||
dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
|
||||
list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
|
||||
InstrItinClass Itinerary = itin;
|
||||
bit hasSideEffects = 1;
|
||||
}
|
||||
class SHLL_PH_MM_DESC : SHLL_R2_MM_DESC_BASE<
|
||||
"shll.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>,
|
||||
Defs<[DSPOutFlag22]>;
|
||||
class SHLL_S_PH_MM_DESC : SHLL_R2_MM_DESC_BASE<
|
||||
"shll_s.ph", int_mips_shll_s_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>,
|
||||
Defs<[DSPOutFlag22]>;
|
||||
class SHLL_QB_MM_DESC : SHLL_R2_MM_DESC_BASE<
|
||||
"shll.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>,
|
||||
Defs<[DSPOutFlag22]>;
|
||||
class SHLL_S_W_MM_DESC : SHLL_R2_MM_DESC_BASE<
|
||||
"shll_s.w", int_mips_shll_s_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>,
|
||||
Defs<[DSPOutFlag22]>;
|
||||
class SHRA_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE<
|
||||
"shra.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>;
|
||||
class SHRA_R_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE<
|
||||
"shra_r.qb", int_mips_shra_r_qb, immZExt3, NoItinerary, DSPROpnd, uimm3>;
|
||||
|
||||
class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
InstrItinClass itin, RegisterOperand RO> {
|
||||
dag OutOperandList = (outs RO:$rd);
|
||||
dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs");
|
||||
list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
class SHLLV_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE<
|
||||
"shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
|
||||
class SHLLV_S_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE<
|
||||
"shllv_s.ph", int_mips_shll_s_ph, NoItinerary, DSPROpnd>,
|
||||
Defs<[DSPOutFlag22]>;
|
||||
class SHLLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE<
|
||||
"shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
|
||||
class SHLLV_S_W_MM_DESC : SHLLV_R3_MM_DESC_BASE<
|
||||
"shllv_s.w", int_mips_shll_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag22]>;
|
||||
|
||||
// Instruction defs.
|
||||
// microMIPS DSP Rev 1
|
||||
def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
|
||||
def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC;
|
||||
@ -84,6 +140,14 @@ def MSUB_DSP_MM : DspMMRel, MSUB_DSP_MM_ENC, MSUB_DSP_DESC;
|
||||
def MSUBU_DSP_MM : DspMMRel, MSUBU_DSP_MM_ENC, MSUBU_DSP_DESC;
|
||||
def MULT_DSP_MM : DspMMRel, MULT_DSP_MM_ENC, MULT_DSP_DESC;
|
||||
def MULTU_DSP_MM : DspMMRel, MULTU_DSP_MM_ENC, MULTU_DSP_DESC;
|
||||
def SHLL_PH_MM : DspMMRel, SHLL_PH_MM_ENC, SHLL_PH_MM_DESC;
|
||||
def SHLL_S_PH_MM : DspMMRel, SHLL_S_PH_MM_ENC, SHLL_S_PH_MM_DESC;
|
||||
def SHLL_QB_MM : DspMMRel, SHLL_QB_MM_ENC, SHLL_QB_MM_DESC;
|
||||
def SHLLV_PH_MM : DspMMRel, SHLLV_PH_MM_ENC, SHLLV_PH_MM_DESC;
|
||||
def SHLLV_S_PH_MM : DspMMRel, SHLLV_S_PH_MM_ENC, SHLLV_S_PH_MM_DESC;
|
||||
def SHLLV_QB_MM : DspMMRel, SHLLV_QB_MM_ENC, SHLLV_QB_MM_DESC;
|
||||
def SHLLV_S_W_MM : DspMMRel, SHLLV_S_W_MM_ENC, SHLLV_S_W_MM_DESC;
|
||||
def SHLL_S_W_MM : DspMMRel, SHLL_S_W_MM_ENC, SHLL_S_W_MM_DESC;
|
||||
// microMIPS DSP Rev 2
|
||||
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
|
||||
ISA_DSPR2;
|
||||
@ -101,3 +165,6 @@ def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
|
||||
def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
|
||||
ISA_DSPR2;
|
||||
def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
|
||||
def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2;
|
||||
def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC,
|
||||
ISA_DSPR2;
|
||||
|
||||
@ -335,6 +335,7 @@ class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
|
||||
list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
|
||||
InstrItinClass Itinerary = itin;
|
||||
string BaseOpcode = instr_asm;
|
||||
}
|
||||
|
||||
class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
@ -346,6 +347,7 @@ class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
|
||||
InstrItinClass Itinerary = itin;
|
||||
bit hasSideEffects = 1;
|
||||
string BaseOpcode = instr_asm;
|
||||
}
|
||||
|
||||
class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
@ -1110,20 +1112,20 @@ def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
|
||||
def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
|
||||
def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
|
||||
def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
|
||||
def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
|
||||
def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
|
||||
def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
|
||||
def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
|
||||
def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
|
||||
def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
|
||||
def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
|
||||
def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
|
||||
def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
|
||||
def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
|
||||
def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
|
||||
def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
|
||||
def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
|
||||
def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
|
||||
def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
|
||||
def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
|
||||
def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
|
||||
def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
|
||||
def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
|
||||
def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
|
||||
def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
|
||||
def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
|
||||
def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
|
||||
def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
|
||||
def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
|
||||
@ -1234,9 +1236,9 @@ def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
|
||||
def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
|
||||
def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
|
||||
def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
|
||||
def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
|
||||
def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
|
||||
def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
|
||||
def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
|
||||
def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
|
||||
def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
|
||||
def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
|
||||
def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
|
||||
|
||||
@ -20,3 +20,11 @@
|
||||
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
|
||||
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
|
||||
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
|
||||
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
|
||||
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
|
||||
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
|
||||
0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5
|
||||
0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5
|
||||
0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5
|
||||
0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5
|
||||
0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5
|
||||
|
||||
@ -13,3 +13,5 @@
|
||||
0x00 0xec 0xe2 0xbc # CHECK: dpaqx_s.w.ph $ac3, $12, $7
|
||||
0x00 0xc5 0x32 0xbc # CHECK: dpaqx_sa.w.ph $ac0, $5, $6
|
||||
0x00 0x22 0xd0 0xbc # CHECK: dpax.w.ph $ac3, $2, $1
|
||||
0x00 0x64 0xa1 0xfc # CHECK: shra.qb $3, $4, 5
|
||||
0x00 0x64 0xb1 0xfc # CHECK: shra_r.qb $3, $4, 5
|
||||
|
||||
@ -21,3 +21,11 @@
|
||||
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
|
||||
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
|
||||
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
|
||||
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
|
||||
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
|
||||
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
|
||||
shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e]
|
||||
shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e]
|
||||
shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95]
|
||||
shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5]
|
||||
shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5]
|
||||
|
||||
@ -14,3 +14,5 @@
|
||||
dpaqx_s.w.ph $ac3, $12, $7 # CHECK: dpaqx_s.w.ph $ac3, $12, $7 # encoding: [0x00,0xec,0xe2,0xbc]
|
||||
dpaqx_sa.w.ph $ac0, $5, $6 # CHECK: dpaqx_sa.w.ph $ac0, $5, $6 # encoding: [0x00,0xc5,0x32,0xbc]
|
||||
dpax.w.ph $ac3, $2, $1 # CHECK: dpax.w.ph $ac3, $2, $1 # encoding: [0x00,0x22,0xd0,0xbc]
|
||||
shra.qb $3, $4, 5 # CHECK: shra.qb $3, $4, 5 # encoding: [0x00,0x64,0xa1,0xfc]
|
||||
shra_r.qb $3, $4, 5 # CHECK: shra_r.qb $3, $4, 5 # encoding: [0x00,0x64,0xb1,0xfc]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user