mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 20:23:11 +01:00
Revert "[HWASan] Use page aliasing on x86_64."
This reverts commit 63f73c3eb9716256ab8dbb868e16d08a88636cba due to breakage on aarch64 without TBI.
This commit is contained in:
parent
4391957539
commit
704ca6ef7f
@ -708,7 +708,7 @@ static size_t TypeSizeToSizeIndex(uint32_t TypeSize) {
|
||||
}
|
||||
|
||||
void HWAddressSanitizer::untagPointerOperand(Instruction *I, Value *Addr) {
|
||||
if (TargetTriple.isAArch64() || TargetTriple.getArch() == Triple::x86_64)
|
||||
if (TargetTriple.isAArch64())
|
||||
return;
|
||||
|
||||
IRBuilder<> IRB(I);
|
||||
@ -1004,7 +1004,6 @@ Value *HWAddressSanitizer::tagPointer(IRBuilder<> &IRB, Type *Ty,
|
||||
|
||||
// Remove tag from an address.
|
||||
Value *HWAddressSanitizer::untagPointer(IRBuilder<> &IRB, Value *PtrLong) {
|
||||
assert(!UsePageAliases);
|
||||
Value *UntaggedPtrLong;
|
||||
if (CompileKernel) {
|
||||
// Kernel addresses have 0xFF in the most significant byte.
|
||||
|
@ -11,7 +11,10 @@ define void @atomicrmw(i64* %ptr) sanitize_hwaddress {
|
||||
|
||||
; CHECK: call void @__hwasan_store8(i64 %[[A]])
|
||||
|
||||
; CHECK: atomicrmw add i64* %ptr, i64 1 seq_cst
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i64* %ptr to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i64*
|
||||
; CHECK: atomicrmw add i64* %[[UNTAGGED_PTR]], i64 1 seq_cst
|
||||
; CHECK: ret void
|
||||
|
||||
entry:
|
||||
@ -25,7 +28,10 @@ define void @cmpxchg(i64* %ptr, i64 %compare_to, i64 %new_value) sanitize_hwaddr
|
||||
|
||||
; CHECK: call void @__hwasan_store8(i64 %[[A]])
|
||||
|
||||
; CHECK: cmpxchg i64* %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i64* %ptr to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i64*
|
||||
; CHECK: cmpxchg i64* %[[UNTAGGED_PTR]], i64 %compare_to, i64 %new_value seq_cst seq_cst
|
||||
; CHECK: ret void
|
||||
|
||||
entry:
|
||||
|
@ -15,7 +15,10 @@ define i8 @test_load8(i8* %a) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_load1(i64 %[[A]])
|
||||
; RECOVER: call void @__hwasan_load1_noabort(i64 %[[A]])
|
||||
|
||||
; CHECK: %[[G:[^ ]*]] = load i8, i8* %a, align 4
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i8*
|
||||
; CHECK: %[[G:[^ ]*]] = load i8, i8* %[[UNTAGGED_PTR]], align 4
|
||||
; CHECK: ret i8 %[[G]]
|
||||
|
||||
entry:
|
||||
@ -30,7 +33,10 @@ define i40 @test_load40(i40* %a) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_loadN(i64 %[[A]], i64 5)
|
||||
; RECOVER: call void @__hwasan_loadN_noabort(i64 %[[A]], i64 5)
|
||||
|
||||
; CHECK: %[[B:[^ ]*]] = load i40, i40* %a
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i40*
|
||||
; CHECK: %[[B:[^ ]*]] = load i40, i40* %[[UNTAGGED_PTR]]
|
||||
; CHECK: ret i40 %[[B]]
|
||||
|
||||
entry:
|
||||
@ -45,7 +51,10 @@ define void @test_store8(i8* %a, i8 %b) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_store1(i64 %[[A]])
|
||||
; RECOVER: call void @__hwasan_store1_noabort(i64 %[[A]])
|
||||
|
||||
; CHECK: store i8 %b, i8* %a, align 4
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i8*
|
||||
; CHECK: store i8 %b, i8* %[[UNTAGGED_PTR]], align 4
|
||||
; CHECK: ret void
|
||||
|
||||
entry:
|
||||
@ -60,7 +69,10 @@ define void @test_store40(i40* %a, i40 %b) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 5)
|
||||
; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 5)
|
||||
|
||||
; CHECK: store i40 %b, i40* %a
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i40*
|
||||
; CHECK: store i40 %b, i40* %[[UNTAGGED_PTR]]
|
||||
; CHECK: ret void
|
||||
|
||||
entry:
|
||||
@ -75,7 +87,10 @@ define void @test_store_unaligned(i64* %a, i64 %b) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 8)
|
||||
; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 8)
|
||||
|
||||
; CHECK: store i64 %b, i64* %a, align 4
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i64* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i64*
|
||||
; CHECK: store i64 %b, i64* %[[UNTAGGED_PTR]], align 4
|
||||
; CHECK: ret void
|
||||
|
||||
entry:
|
||||
|
@ -18,7 +18,10 @@ define i8 @test_load(i8* %a) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_load1(i64 %[[A]])
|
||||
; RECOVER: call void @__hwasan_load1_noabort(i64 %[[A]])
|
||||
|
||||
; CHECK: %[[G:[^ ]*]] = load i8, i8* %a, align 4
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = or i64 %[[A]], -72057594037927936
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i8*
|
||||
; CHECK: %[[G:[^ ]*]] = load i8, i8* %[[UNTAGGED_PTR]], align 4
|
||||
; CHECK: ret i8 %[[G]]
|
||||
|
||||
entry:
|
||||
|
@ -13,7 +13,10 @@ define i8 @test_load8(i8* %a) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_load1(i64 %[[A]])
|
||||
; RECOVER: call void @__hwasan_load1_noabort(i64 %[[A]])
|
||||
|
||||
; CHECK: %[[B:[^ ]*]] = load i8, i8* %a
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i8*
|
||||
; CHECK: %[[B:[^ ]*]] = load i8, i8* %[[UNTAGGED_PTR]]
|
||||
; CHECK: ret i8 %[[B]]
|
||||
|
||||
entry:
|
||||
@ -28,7 +31,10 @@ define i40 @test_load40(i40* %a) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_loadN(i64 %[[A]], i64 5)
|
||||
; RECOVER: call void @__hwasan_loadN_noabort(i64 %[[A]], i64 5)
|
||||
|
||||
; CHECK: %[[B:[^ ]*]] = load i40, i40* %a
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i40*
|
||||
; CHECK: %[[B:[^ ]*]] = load i40, i40* %[[UNTAGGED_PTR]]
|
||||
; CHECK: ret i40 %[[B]]
|
||||
|
||||
entry:
|
||||
@ -43,7 +49,10 @@ define void @test_store8(i8* %a, i8 %b) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_store1(i64 %[[A]])
|
||||
; RECOVER: call void @__hwasan_store1_noabort(i64 %[[A]])
|
||||
|
||||
; CHECK: store i8 %b, i8* %a
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i8*
|
||||
; CHECK: store i8 %b, i8* %[[UNTAGGED_PTR]]
|
||||
; CHECK: ret void
|
||||
|
||||
entry:
|
||||
@ -58,7 +67,10 @@ define void @test_store40(i40* %a, i40 %b) sanitize_hwaddress {
|
||||
; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 5)
|
||||
; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 5)
|
||||
|
||||
; CHECK: store i40 %b, i40* %a
|
||||
; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64
|
||||
; CHECK: %[[UNTAGGED:[^ ]*]] = and i64 %[[A]], 72057594037927935
|
||||
; CHECK: %[[UNTAGGED_PTR:[^ ]*]] = inttoptr i64 %[[UNTAGGED]] to i40*
|
||||
; CHECK: store i40 %b, i40* %[[UNTAGGED_PTR]]
|
||||
; CHECK: ret void
|
||||
|
||||
entry:
|
||||
|
Loading…
Reference in New Issue
Block a user