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[AMDGPU] Pre-commit test case for D106284

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This test case shows the scheduler wrongly reordering two buffer
accesses that might alias.
This commit is contained in:
Jay Foad 2021-07-19 16:20:44 +01:00
parent 7d0a83254c
commit 70ace9e728
1 changed files with 18 additions and 1 deletions
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19
test/CodeGen/AMDGPU/buffer-schedule.ll
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@ -44,10 +44,27 @@ define amdgpu_cs void @_amdgpu_cs_main(<3 x i32> inreg %arg3, <3 x i32> %arg5) {
ret void
}
; FIXME: the first load and store should not be reordered because they might
; alias depending on the value of %off
; GCN-LABEL: {{^}}test1:
; GCN: buffer_load_dword
; GCN: buffer_store_dword
; GCN: buffer_store_dword
define amdgpu_cs void @test1(<4 x i32> inreg %buf, i32 %off) {
.entry:
call void @llvm.amdgcn.raw.buffer.store.i32(i32 0, <4 x i32> %buf, i32 8, i32 0, i32 0)
%val = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %buf, i32 %off, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.store.i32(i32 %val, <4 x i32> %buf, i32 0, i32 0, i32 0)
ret void
}
declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #2
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #3
declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #2
declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) #3
attributes #2 = { nounwind readonly }
attributes #3 = { nounwind writeonly }