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Mips64 arithmetic and logical instructions with two source registers.

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llvm-svn: 140806
This commit is contained in:
Akira Hatanaka 2011-09-29 20:37:56 +00:00
parent ac33381aa1
commit 70be05d5d0
2 changed files with 66 additions and 0 deletions
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30
lib/Target/Mips/Mips64InstrInfo.td
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@ -17,3 +17,33 @@
def HasMips64 : Predicate<"Subtarget.hasMips64()">;
def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
//===----------------------------------------------------------------------===//
// Instructions specific format
//===----------------------------------------------------------------------===//
// Arithmetic 3 register operands
class ArithR64<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
InstrItinClass itin, bit isComm = 0>:
FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], itin> {
let isCommutable = isComm;
}
// Logical
let isCommutable = 1 in
class LogicR64<bits<6> func, string instr_asm, SDNode OpNode>:
FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu>;
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
/// Arithmetic Instructions (3-Operand, R-Type)
def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu, 1>;
def DAND : LogicR64<0x24, "and", and>;
def DOR : LogicR64<0x25, "or", or>;
def DXOR : LogicR64<0x26, "xor", xor>;

36
test/CodeGen/Mips/mips64instrs.ll Normal file
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@ -0,0 +1,36 @@
; RUN: llc -march=mips64el -mcpu=mips64r1 < %s | FileCheck %s
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: daddu
%add = add nsw i64 %a1, %a0
ret i64 %add
}
define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: dsubu
%sub = sub nsw i64 %a0, %a1
ret i64 %sub
}
define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: and
%and = and i64 %a1, %a0
ret i64 %and
}
define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: or
%or = or i64 %a1, %a0
ret i64 %or
}
define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: xor
%xor = xor i64 %a1, %a0
ret i64 %xor
}