diff --git a/lib/Target/Sparc/SparcInstrAliases.td b/lib/Target/Sparc/SparcInstrAliases.td
index 4a0e8c856f2..8c528fca6a5 100644
--- a/lib/Target/Sparc/SparcInstrAliases.td
+++ b/lib/Target/Sparc/SparcInstrAliases.td
@@ -521,3 +521,6 @@ def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<
 
 // signx reg, rd -> sra reg, %g0, rd
 def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;
+
+// sir -> sir 0
+def : InstAlias<"sir", (SIR 0), 0>;
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index d1190ae03d2..5e41ff51204 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -1534,6 +1534,11 @@ let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
  def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13),
                     "membar $simm13", []>;
 
+let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in
+  def SIR: F3_2<2, 0b110000, (outs),
+                (ins simm13Op:$simm13),
+                 "sir $simm13", []>;
+
 // The CAS instruction, unlike other instructions, only comes in a
 // form which requires an ASI be provided. The ASI value hardcoded
 // here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.
diff --git a/test/MC/Sparc/sparc-v9-traps.s b/test/MC/Sparc/sparc-v9-traps.s
index da11b36003b..8e5a48794ec 100644
--- a/test/MC/Sparc/sparc-v9-traps.s
+++ b/test/MC/Sparc/sparc-v9-traps.s
@@ -300,4 +300,8 @@
         tvs %xcc, 82
         tvs %xcc, %g1 + %i2
         tvs %xcc, %i5 + 41
-      
\ No newline at end of file
+
+        ! CHECK: sir 0                  ! encoding: [0x9f,0x80,0x20,0x00]
+        ! CHECK: sir 123                ! encoding: [0x9f,0x80,0x20,0x7b]
+        sir
+        sir 123