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Implementation of 16-bit microMIPS instructions MFHI and MFLO.

Browse Source 
Differential Revision: http://llvm-reviews.chandlerc.com/D3141

llvm-svn: 205532
This commit is contained in:
Zoran Jovanovic 2014-04-03 12:47:34 +00:00
parent baa1451096
commit 712fef1943
5 changed files with 40 additions and 7 deletions
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10
lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -62,6 +62,16 @@ class JALR_FM_MM16<bits<5> op> {
let Inst{4-0} = rs;
}
class MFHILO_FM_MM16<bits<5> funct> {
bits<5> rd;
bits<16> Inst;
let Inst{15-10} = 0x11;
let Inst{9-5} = funct;
let Inst{4-0} = rd;
}
//===----------------------------------------------------------------------===//
// MicroMIPS 32-bit Instruction Formats
//===----------------------------------------------------------------------===//

9
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -70,6 +70,13 @@ class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
let mayLoad = 1;
}
class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
[], II_MFHI_MFLO, FrmR> {
let Uses = [UseReg];
let hasSideEffects = 0;
}
class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
InstrItinClass Itin = NoItinerary> :
MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
@ -87,6 +94,8 @@ class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
let Defs = [RA];
}
def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;

2
lib/Target/Mips/MipsInstrInfo.td
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@ -1102,8 +1102,10 @@ def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
let Predicates = [NotInMicroMips] in {
def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
}
/// Sign Ext In Register Instructions.
def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;

20
lib/Target/Mips/MipsSEInstrInfo.cpp
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@ -96,11 +96,13 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = Mips::CFC1;
else if (Mips::FGR32RegClass.contains(SrcReg))
Opc = Mips::MFC1;
else if (Mips::HI32RegClass.contains(SrcReg))
Opc = Mips::MFHI, SrcReg = 0;
else if (Mips::LO32RegClass.contains(SrcReg))
Opc = Mips::MFLO, SrcReg = 0;
else if (Mips::HI32DSPRegClass.contains(SrcReg))
else if (Mips::HI32RegClass.contains(SrcReg)) {
Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
SrcReg = 0;
} else if (Mips::LO32RegClass.contains(SrcReg)) {
Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
SrcReg = 0;
} else if (Mips::HI32DSPRegClass.contains(SrcReg))
Opc = Mips::MFHI_DSP;
else if (Mips::LO32DSPRegClass.contains(SrcReg))
Opc = Mips::MFLO_DSP;
@ -263,6 +265,8 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
MachineBasicBlock &MBB = *MI->getParent();
bool isMicroMips = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode();
unsigned Opc;
switch(MI->getDesc().getOpcode()) {
default:
@ -271,10 +275,12 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
expandRetRA(MBB, MI, Mips::RET);
break;
case Mips::PseudoMFHI:
expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
expandPseudoMFHiLo(MBB, MI, Opc);
break;
case Mips::PseudoMFLO:
expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
expandPseudoMFHiLo(MBB, MI, Opc);
break;
case Mips::PseudoMFHI64:
expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);

6
test/MC/Mips/micromips-16-bit-instructions.s
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@ -9,13 +9,19 @@
#------------------------------------------------------------------------------
# Little endian
#------------------------------------------------------------------------------
# CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
# CHECK-EL: mflo $9 # encoding: [0x49,0x46]
# CHECK-EL: move $25, $1 # encoding: [0x21,0x0f]
# CHECK-EL: jalr $9 # encoding: [0xc9,0x45]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
# CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
# CHECK-EB: mflo $9 # encoding: [0x46,0x49]
# CHECK-EB: move $25, $1 # encoding: [0x0f,0x21]
# CHECK-EB: jalr $9 # encoding: [0x45,0xc9]
mfhi $9
mflo $9
move $25, $1
jalr $9