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AMDGPU/GlobalISel: Remove old hacks for boolean selection
There were various hacks used to try to avoid making s1 SGPR vs. s1 VCC ambiguous after constraining the register before we had a strategy to deal with this. This also attempted to handle undef operands, which are now illegal gMIR.
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7371d3a454
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@ -170,19 +170,6 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
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if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI))
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return false;
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// Don't constrain the source register to a class so the def instruction
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// handles it (unless it's undef).
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//
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// FIXME: This is a hack. When selecting the def, we neeed to know
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// specifically know that the result is VCCRegBank, and not just an SGPR
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// with size 1. An SReg_32 with size 1 is ambiguous with wave32.
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if (Src.isUndef()) {
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const TargetRegisterClass *SrcRC =
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TRI.getConstrainedRegClassForOperand(Src, *MRI);
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if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
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return false;
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}
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return true;
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}
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@ -286,50 +273,24 @@ static unsigned getLogicalBitOpcode(unsigned Opc, bool Is64) {
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}
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bool AMDGPUInstructionSelector::selectG_AND_OR_XOR(MachineInstr &I) const {
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MachineOperand &Dst = I.getOperand(0);
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MachineOperand &Src0 = I.getOperand(1);
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MachineOperand &Src1 = I.getOperand(2);
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Register DstReg = Dst.getReg();
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Register DstReg = I.getOperand(0).getReg();
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unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI);
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const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
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if (DstRB->getID() == AMDGPU::VCCRegBankID) {
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const TargetRegisterClass *RC = TRI.getBoolRC();
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unsigned InstOpc = getLogicalBitOpcode(I.getOpcode(),
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RC == &AMDGPU::SReg_64RegClass);
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I.setDesc(TII.get(InstOpc));
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// Dead implicit-def of scc
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I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
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true, // isImp
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false, // isKill
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true)); // isDead
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if (DstRB->getID() != AMDGPU::SGPRRegBankID &&
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DstRB->getID() != AMDGPU::VCCRegBankID)
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return false;
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// FIXME: Hack to avoid turning the register bank into a register class.
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// The selector for G_ICMP relies on seeing the register bank for the result
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// is VCC. In wave32 if we constrain the registers to SReg_32 here, it will
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// be ambiguous whether it's a scalar or vector bool.
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if (Src0.isUndef() && !MRI->getRegClassOrNull(Src0.getReg()))
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MRI->setRegClass(Src0.getReg(), RC);
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if (Src1.isUndef() && !MRI->getRegClassOrNull(Src1.getReg()))
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MRI->setRegClass(Src1.getReg(), RC);
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bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID &&
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STI.isWave64());
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I.setDesc(TII.get(getLogicalBitOpcode(I.getOpcode(), Is64)));
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return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
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}
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// TODO: Should this allow an SCC bank result, and produce a copy from SCC for
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// the result?
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if (DstRB->getID() == AMDGPU::SGPRRegBankID) {
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unsigned InstOpc = getLogicalBitOpcode(I.getOpcode(), Size > 32);
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I.setDesc(TII.get(InstOpc));
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// Dead implicit-def of scc
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I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
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true, // isImp
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false, // isKill
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true)); // isDead
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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return false;
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// Dead implicit-def of scc
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I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
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true, // isImp
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false, // isKill
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true)); // isDead
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
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@ -2338,8 +2299,7 @@ bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
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CondPhysReg = AMDGPU::SCC;
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BrOpcode = AMDGPU::S_CBRANCH_SCC1;
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// FIXME: Hack for isSCC tests
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ConstrainRC = &AMDGPU::SGPR_32RegClass;
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ConstrainRC = &AMDGPU::SReg_32RegClass;
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} else {
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// FIXME: Do we have to insert an and with exec here, like in SelectionDAG?
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// We sort of know that a VCC producer based on the register bank, that ands
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@ -1210,6 +1210,10 @@ public:
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return getWavefrontSize() == 32;
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}
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bool isWave64() const {
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return getWavefrontSize() == 64;
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}
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const TargetRegisterClass *getBoolRC() const {
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return getRegisterInfo()->getBoolRC();
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}
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@ -20,7 +20,7 @@ body: |
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY2]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: bb.1:
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@ -46,7 +46,7 @@ body: |
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; GCN-LABEL: name: brcond_scc_impdef
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
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; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN: $scc = COPY [[DEF]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: bb.1:
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@ -73,7 +73,7 @@ body: |
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY2]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.1
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@ -17,7 +17,7 @@ body: |
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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@ -66,7 +66,7 @@ body: |
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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@ -116,7 +116,7 @@ body: |
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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@ -165,7 +165,7 @@ body: |
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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@ -215,7 +215,7 @@ body: |
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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@ -263,7 +263,7 @@ body: |
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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@ -314,7 +314,7 @@ body: |
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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@ -363,7 +363,7 @@ body: |
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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@ -412,7 +412,7 @@ body: |
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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