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Fix ModR/M byte output for 16-bit addressing modes (PR18220)
Add some tests to validate correct register selection, including a fix to an existing test which was requiring the *wrong* output. Patch from David Woodhouse. llvm-svn: 198566
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@ -402,6 +402,66 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
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// 16-bit addressing forms of the ModR/M byte have a different encoding for
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// the R/M field and are far more limited in which registers can be used.
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if (Is16BitMemOperand(MI, Op)) {
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if (BaseReg) {
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// For 32-bit addressing, the row and column values in Table 2-2 are
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// basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
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// some special cases. And GetX86RegNum reflects that numbering.
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// For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
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// Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
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// use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
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// while values 0-3 indicate the allowed combinations (base+index) of
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// those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
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//
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// R16Table[] is a lookup from the normal RegNo, to the row values from
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// Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
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static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
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unsigned RMfield = R16Table[BaseRegNo];
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assert(RMfield && "invalid 16-bit base register");
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if (IndexReg.getReg()) {
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unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
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assert(IndexReg16 && "invalid 16-bit index register");
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// We must have one of SI/DI (4,5), and one of BP/BX (6,7).
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assert(((IndexReg16 ^ RMfield) & 2) &&
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"invalid 16-bit base/index register combination");
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assert(Scale.getImm() == 1 &&
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"invalid scale for 16-bit memory reference");
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// Allow base/index to appear in either order (although GAS doesn't).
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if (IndexReg16 & 2)
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RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
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else
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RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
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}
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if (Disp.isImm() && isDisp8(Disp.getImm())) {
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if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
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// There is no displacement; just the register.
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EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
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return;
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}
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// Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
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EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
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EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
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return;
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}
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// This is the [REG]+disp16 case.
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EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
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} else {
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// There is no BaseReg; this is the plain [disp16] case.
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EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
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}
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// Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
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EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
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return;
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}
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// Determine whether a SIB byte is needed.
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// If no BaseReg, issue a RIP relative instruction only if the MCE can
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// resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
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@ -8,6 +8,12 @@
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.code32
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movb $0x0, (%si)
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// CHECK: encoding: [0x67,0xc6,0x06,0x00]
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// CHECK: encoding: [0x67,0xc6,0x04,0x00]
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movb $0x0, (%esi)
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// CHECK: encoding: [0xc6,0x06,0x00]
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movw $0x1234, (%si)
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// CHECK: encoding: [0x67,0x66,0xc7,0x04,0x34,0x12]
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movl $0x12345678, (%bx,%si,1)
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// CHECK: encoding: [0x67,0xc7,0x00,0x78,0x56,0x34,0x12]
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movw $0x1234, 0x5678(%bp)
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// CHECK: encoding: [0x67,0x66,0xc7,0x86,0x78,0x56,0x34,0x12]
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