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Hexagon: Set accessSize and addrMode on all load/store instructions.
llvm-svn: 181324
This commit is contained in:
Jyotsna Verma
parent
25056babb2
commit
71c6bf55f2
@ -54,6 +54,7 @@ def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
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def BaseImmOffset : AddrModeType<3>; // Indirect with offset
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def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
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def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
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def PostInc : AddrModeType<6>; // Post increment addressing mode
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class MemAccessSize<bits<3> value> {
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bits<3> Value = value;
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@ -932,12 +932,21 @@ multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
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}
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let addrMode = BaseImmOffset, isMEMri = "true" in {
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defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
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defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
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defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
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defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
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defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
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defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
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let accessSize = ByteAccess in {
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defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
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defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
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}
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let accessSize = HalfWordAccess in {
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defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
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defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
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}
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let accessSize = WordAccess in
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defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
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let accessSize = DoubleWordAccess in
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defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
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}
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def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
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@ -1000,18 +1009,25 @@ multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
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}
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let addrMode = BaseImmOffset in {
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defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
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11, 6>, AddrModeRel;
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defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
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11, 6>, AddrModeRel;
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defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
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12, 7>, AddrModeRel;
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defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
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12, 7>, AddrModeRel;
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defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
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13, 8>, AddrModeRel;
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defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
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14, 9>, AddrModeRel;
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let accessSize = ByteAccess in {
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defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
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11, 6>, AddrModeRel;
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defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
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11, 6>, AddrModeRel;
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}
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let accessSize = HalfWordAccess in {
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defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
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12, 7>, AddrModeRel;
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defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
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12, 7>, AddrModeRel;
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}
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let accessSize = WordAccess in
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defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
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13, 8>, AddrModeRel;
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let accessSize = DoubleWordAccess in
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defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
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14, 9>, AddrModeRel;
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}
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let AddedComplexity = 20 in {
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@ -1036,8 +1052,6 @@ def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
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//===----------------------------------------------------------------------===//
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// Post increment load
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// Make sure that in post increment load, the first operand is always the post
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// increment operand.
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//===----------------------------------------------------------------------===//
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multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
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@ -1079,7 +1093,7 @@ multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
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}
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}
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let hasCtrlDep = 1, neverHasSideEffects = 1 in {
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let hasCtrlDep = 1, neverHasSideEffects = 1, addrMode = PostInc in {
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defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
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PredNewRel;
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defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
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@ -1382,7 +1396,7 @@ multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
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multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
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Operand ImmOp, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME# : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
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defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
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// Predicate new
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let Predicates = [HasV4T], validSubTargets = HasV4SubT in
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defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
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@ -1397,7 +1411,7 @@ multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
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let isPredicable = 1 in
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def NAME : STInst2PI<(outs IntRegs:$dst),
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(ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
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#mnemonic#"($src1++#$offset) = $src2",
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mnemonic#"($src1++#$offset) = $src2",
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[],
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"$src1 = $dst">;
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@ -1474,12 +1488,17 @@ multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
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}
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let addrMode = BaseImmOffset, isMEMri = "true" in {
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defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
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defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
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defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
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let accessSize = ByteAccess in
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defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
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let isNVStorable = 0 in
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defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
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let accessSize = HalfWordAccess in
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defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
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let accessSize = WordAccess in
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defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
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let accessSize = DoubleWordAccess, isNVStorable = 0 in
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defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
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}
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def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
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@ -1541,15 +1560,21 @@ multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
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}
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let addrMode = BaseImmOffset, InputType = "reg" in {
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defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
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u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
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defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
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u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
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defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
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u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
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let isNVStorable = 0 in
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defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
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u6_3Ext, 14, 9>, AddrModeRel;
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let accessSize = ByteAccess in
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defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
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u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
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let accessSize = HalfWordAccess in
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defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
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u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
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let accessSize = WordAccess in
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defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
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u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
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let accessSize = DoubleWordAccess, isNVStorable = 0 in
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defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
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u6_3Ext, 14, 9>, AddrModeRel;
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}
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let AddedComplexity = 10 in {
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@ -213,7 +213,7 @@ def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
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// Template class for load instructions with Absolute set addressing mode.
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//===----------------------------------------------------------------------===//
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let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
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validSubTargets = HasV4SubT in
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validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
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class T_LD_abs_set<string mnemonic, RegisterClass RC>:
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LDInst2<(outs RC:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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@ -266,12 +266,23 @@ multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
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}
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let addrMode = BaseRegOffset in {
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defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
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defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
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defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
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defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
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defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
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defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
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let accessSize = ByteAccess in {
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defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>,
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AddrModeRel;
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defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>,
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AddrModeRel;
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}
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let accessSize = HalfWordAccess in {
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defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
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defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>,
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AddrModeRel;
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}
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let accessSize = WordAccess in
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defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
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let accessSize = DoubleWordAccess in
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defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>,
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AddrModeRel;
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}
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// 'def pats' for load instructions with base + register offset and non-zero
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@ -456,7 +467,8 @@ def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
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//===----------------------------------------------------------------------===//
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// Template class for store instructions with Absolute set addressing mode.
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//===----------------------------------------------------------------------===//
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let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
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let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT,
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addrMode = AbsoluteSet in
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class T_ST_abs_set<string mnemonic, RegisterClass RC>:
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STInst2<(outs IntRegs:$dst1),
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(ins RC:$src1, u0AlwaysExt:$src2),
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@ -551,17 +563,20 @@ multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
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let addrMode = BaseRegOffset, neverHasSideEffects = 1,
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validSubTargets = HasV4SubT in {
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defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
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ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
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let accessSize = ByteAccess in
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defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
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ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
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defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
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ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
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let accessSize = HalfWordAccess in
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defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
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ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
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defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
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ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
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let accessSize = WordAccess in
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defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
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ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
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let isNVStorable = 0 in
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defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
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let isNVStorable = 0, accessSize = DoubleWordAccess in
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defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
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}
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let Predicates = [HasV4T], AddedComplexity = 10 in {
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@ -695,10 +710,15 @@ multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
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}
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let addrMode = BaseImmOffset, InputType = "imm",
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validSubTargets = HasV4SubT in {
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defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
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defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
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defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
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validSubTargets = HasV4SubT in {
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let accessSize = ByteAccess in
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defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
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let accessSize = HalfWordAccess in
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defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
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let accessSize = WordAccess in
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defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
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}
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let Predicates = [HasV4T], AddedComplexity = 10 in {
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@ -834,12 +854,17 @@ multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
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}
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let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
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defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
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u6_0Ext, 11, 6>, AddrModeRel;
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defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
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u6_1Ext, 12, 7>, AddrModeRel;
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defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
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u6_2Ext, 13, 8>, AddrModeRel;
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let accessSize = ByteAccess in
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defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
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u6_0Ext, 11, 6>, AddrModeRel;
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let accessSize = HalfWordAccess in
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defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
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u6_1Ext, 12, 7>, AddrModeRel;
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let accessSize = WordAccess in
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defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
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u6_2Ext, 13, 8>, AddrModeRel;
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}
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// multiclass for new-value store instructions with base + immediate offset.
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@ -887,9 +912,14 @@ multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
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let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
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mayStore = 1 in {
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defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
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defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
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defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
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let accessSize = ByteAccess in
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defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
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let accessSize = HalfWordAccess in
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defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
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let accessSize = WordAccess in
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defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
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}
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//===----------------------------------------------------------------------===//
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@ -939,7 +969,7 @@ multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
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}
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}
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let validSubTargets = HasV4SubT in {
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let addrMode = PostInc, validSubTargets = HasV4SubT in {
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defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
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defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
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defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
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@ -65,7 +65,8 @@ namespace HexagonII {
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AbsoluteSet = 2, // Absolute set addressing mode
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BaseImmOffset = 3, // Indirect with offset
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BaseLongOffset = 4, // Indirect with long offset
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BaseRegOffset = 5 // Indirect with register offset
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BaseRegOffset = 5, // Indirect with register offset
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PostInc = 6 // Post increment addressing mode
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};
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||||
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||||
enum MemAccessSize {
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||||
|
||||
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