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[mips] Properly select abs and sqrt instructions

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- Alter abs for micromips to have both AFGR64 and FGR64
  variants, same as sqrt
- Remove sqrt and abs from MicroMips32r6InstrInfo.td,
  use micromips FGR64 variants
- Restrict non-micromips abs/sqrt with NotInMicroMips
  predicate

Differential revision: https://reviews.llvm.org/D41439

llvm-svn: 323184
This commit is contained in:
Stefan Maksimovic 2018-01-23 10:09:39 +00:00
parent 2a3b64fc69
commit 727b43f54f
29 changed files with 266 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -179,8 +179,6 @@ class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
@ -1042,10 +1040,6 @@ class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
list<Predicate> EncodingPredicates = [HasStdEnc];
}
class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
II_ABS, fabs>;
class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
II_ABS, fabs>;
class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
FGR32Opnd, II_FLOOR>;
class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
@ -1548,8 +1542,6 @@ def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
ISA_MICROMIPS32R6;
defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
@ -1574,10 +1566,6 @@ def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;

27
lib/Target/Mips/MicroMipsInstrFPU.td
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@ -85,11 +85,6 @@ def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd,
ISA_MICROMIPS, FGR_32;
def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32;
def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
fsqrt>, ROUND_W_FM_MM<1, 0x28>,
ISA_MICROMIPS, FGR_32;
def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;
def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
@ -97,11 +92,25 @@ def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
}
multiclass ABSS_MMM<string opstr, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> {
def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
ISA_MICROMIPS, FGR_32 {
string DecoderNamespace = "MicroMips";
}
// FIXME: This needs to be part of the instruction mapping tables.
def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
ISA_MICROMIPS, FGR_64 {
string DecoderNamespace = "MicroMipsFP64";
}
}
defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
let DecoderNamespace = "MicroMips" in {
def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;
def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32;
}
let isCodeGenOnly = 1 in {
@ -184,7 +193,9 @@ def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS;
def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS;
fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS {
string DecoderNamespace = "MicroMips";
}
def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32;
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,

8
lib/Target/Mips/MipsInstrFPU.td
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@ -458,9 +458,11 @@ def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
ABSS_FM<0x7, 16>;
defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
let AdditionalPredicates = [NotInMicroMips] in {
def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
}
// The odd-numbered registers are only referenced when doing loads,
// stores, and moves between floating-point and integer registers.

28
test/CodeGen/Mips/llvm-ir/abs.ll Normal file
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@ -0,0 +1,28 @@
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
define float @abs_s(float %a) {
; MIPS32: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S
; MIPS32FP64: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S
; MM: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM
; MMFP64: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM
; MMR6: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM
%ret = call float @llvm.fabs.f32(float %a)
ret float %ret
}
define double @abs_d(double %a) {
; MIPS32: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D32
; MIPS32FP64: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64
; MM: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D32_MM
; MMFP64: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64_MM
; MMR6: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64_MM
%ret = call double @llvm.fabs.f64(double %a)
ret double %ret
}
declare float @llvm.fabs.f32(float %a)
declare double @llvm.fabs.f64(double %a)

29
test/CodeGen/Mips/llvm-ir/sqrt.ll
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@ -1,6 +1,11 @@
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
define float @sqrt_fn(float %value) #0 {
entry:
@ -11,3 +16,27 @@ entry:
declare float @sqrtf(float)
; CHECK: sqrt.s $f0, $f12
define float @sqrt_s(float %a) {
; MIPS32: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S
; MIPS32FP64: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S
; MM: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S_MM
; MMFP64: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S_MM
; MMR6: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S_MM
%ret = call float @llvm.sqrt.f32(float %a)
ret float %ret
}
define double @sqrt_d(double %a) {
; MIPS32: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D32
; MIPS32FP64: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D64
; MM: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D32_MM
; MMFP64: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D64_MM
; MMR6: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D64_MM
%ret = call double @llvm.sqrt.f64(double %a)
ret double %ret
}
declare float @llvm.sqrt.f32(float %a)
declare double @llvm.sqrt.f64(double %a)

4
test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
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@ -204,3 +204,7 @@
0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30
0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28
0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8
0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12
0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12
0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12
0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt Normal file
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@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
# RUN: | FileCheck %s
0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12
0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12
0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12
0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt Normal file
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@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
# RUN: | FileCheck %s
0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12
0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12
0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12
0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12

4
test/MC/Disassembler/Mips/micromips32r3/valid.txt
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@ -208,3 +208,7 @@
0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30
0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28
0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8
0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12
0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12
0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12
0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt Normal file
View File

@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/mips32/valid-fp64.txt Normal file
View File

@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt Normal file
View File

@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r2 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt Normal file
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@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r2 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt Normal file
View File

@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt Normal file
View File

@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt Normal file
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@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r5 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12

7
test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt Normal file
View File

@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r5 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12

11
test/MC/Mips/micromips/valid-fp64.s Normal file
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@ -0,0 +1,11 @@
# RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -show-encoding -show-inst %s \
# RUN: | FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64_MM

6
test/MC/Mips/micromips/valid.s
View File

@ -52,7 +52,11 @@ lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
abs.s $f0, $f2 # CHECK: abs.s $f0, $f2 # encoding: [0x54,0x02,0x03,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
abs.d $f4, $f6 # CHECK: abs.d $f4, $f6 # encoding: [0x54,0x86,0x23,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_MM
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32_MM
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32_MM
add $9, $6, $7 # CHECK: add $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x10]
addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67]
addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67]

12
test/MC/Mips/micromips32r6/valid.s
View File

@ -215,8 +215,10 @@
cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b]
cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b]
cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b]
abs.s $f3, $f5 # CHECK: abs.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x7b]
abs.d $f2, $f4 # CHECK: abs.d $f2, $f4 # encoding: [0x54,0x44,0x23,0x7b]
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM
floor.l.s $f3, $f5 # CHECK: floor.l.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x3b]
floor.l.d $f2, $f4 # CHECK: floor.l.d $f2, $f4 # encoding: [0x54,0x44,0x43,0x3b]
floor.w.s $f3, $f5 # CHECK: floor.w.s $f3, $f5 # encoding: [0x54,0x65,0x0b,0x3b]
@ -229,8 +231,10 @@
trunc.l.d $f2, $f4 # CHECK: trunc.l.d $f2, $f4 # encoding: [0x54,0x44,0x63,0x3b]
trunc.w.s $f3, $f5 # CHECK: trunc.w.s $f3, $f5 # encoding: [0x54,0x65,0x2b,0x3b]
trunc.w.d $f2, $f4 # CHECK: trunc.w.d $f2, $f4 # encoding: [0x54,0x44,0x6b,0x3b]
sqrt.s $f3, $f5 # CHECK: sqrt.s $f3, $f5 # encoding: [0x54,0x65,0x0a,0x3b]
sqrt.d $f2, $f4 # CHECK: sqrt.d $f2, $f4 # encoding: [0x54,0x44,0x4a,0x3b]
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64_MM
rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b]
rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b]
lw $3, -260($gp) # CHECK: lw $3, -260($gp) # encoding: [0xfc,0x7c,0xfe,0xfc]

8
test/MC/Mips/mips1/valid.s
View File

@ -1,10 +1,12 @@
# Instructions that are valid
#
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips1 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1
add.d $f1,$f7,$f29
add.s $f8,$f21,$f24

14
test/MC/Mips/mips2/valid.s
View File

@ -1,10 +1,12 @@
# Instructions that are valid
#
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips2 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
@ -135,8 +137,10 @@ a:
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]

14
test/MC/Mips/mips32/valid.s
View File

@ -1,10 +1,12 @@
# Instructions that are valid
#
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
@ -193,8 +195,10 @@ a:
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]

11
test/MC/Mips/mips32r2/valid-fp64.s Normal file
View File

@ -0,0 +1,11 @@
# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64

14
test/MC/Mips/mips32r2/valid.s
View File

@ -1,10 +1,12 @@
# Instructions that are valid
#
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r2 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
@ -234,8 +236,10 @@ a:
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]

11
test/MC/Mips/mips32r3/valid-fp64.s Normal file
View File

@ -0,0 +1,11 @@
# RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64

14
test/MC/Mips/mips32r3/valid.s
View File

@ -1,10 +1,12 @@
# Instructions that are valid
#
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | FileCheck %s
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r3 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
@ -234,8 +236,10 @@ a:
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]

11
test/MC/Mips/mips32r5/valid-fp64.s Normal file
View File

@ -0,0 +1,11 @@
# RUN: llvm-mc -arch=mips -mcpu=mips32r5 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64

14
test/MC/Mips/mips32r5/valid.s
View File

@ -1,10 +1,12 @@
# Instructions that are valid
#
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | FileCheck %s
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r5 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
@ -235,8 +237,10 @@ a:
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]