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[mips] Add missing schedinfo for MSA and ASE instructions
llvm-svn: 364757
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@ -515,6 +515,7 @@ class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin>
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class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
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MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
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bit hasNoSchedulingInfo = 1;
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bit usesCustomInserter = 1;
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}
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@ -1239,6 +1239,7 @@ class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
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MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n),
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[(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> {
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bit usesCustomInserter = 1;
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bit hasNoSchedulingInfo = 1;
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}
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class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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@ -1446,6 +1447,7 @@ class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
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[(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
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ROIdx:$n))]> {
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bit usesCustomInserter = 1;
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bit hasNoSchedulingInfo = 1;
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string Constraints = "$wd = $wd_in";
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}
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@ -2043,7 +2045,7 @@ class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
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// 1.0 when we only need to match ISD::FEXP2.
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class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
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class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
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let usesCustomInserter = 1 in {
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let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
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class FEXP2_W_1_PSEUDO_DESC :
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MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
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[(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
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@ -3737,6 +3739,7 @@ class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
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(ins RCWS:$ws),
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[(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
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bit usesCustomInserter = 1;
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bit hasNoSchedulingInfo = 1;
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}
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def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
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@ -3773,7 +3776,7 @@ let ASEPredicate = [HasMSA] in {
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[(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]>;
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}
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let usesCustomInserter = 1 in {
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let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
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def MSA_FP_EXTEND_W_PSEUDO :
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MipsPseudo<(outs FGR32Opnd:$fd), (ins MSA128F16:$ws),
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[(set FGR32Opnd:$fd, (f32 (fpextend MSA128F16:$ws)))]>;
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@ -288,6 +288,8 @@ def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>;
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def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>;
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def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>;
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def : InstRW<[P5600WriteMSAShortInt], (instregex "^BMN*Z.*$")>;
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def : InstRW<[P5600WriteMSAShortInt],
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(instregex "^BSEL_(H|W|D|FW|FD)_PSEUDO$")>;
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// pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd]
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def : InstRW<[P5600WriteMSAOther3], (instregex "^PCNT_[BHWD]$")>;
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@ -335,6 +337,10 @@ def : InstRW<[P5600WriteMSAShortLogic], (instregex "^MOVE_V$")>;
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def : InstRW<[P5600WriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>;
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def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>;
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def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>;
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def : InstRW<[P5600WriteMSAShortLogic],
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(instregex "^(AND|OR|[XN]OR)_V_[DHW]_PSEUDO$")>;
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def : InstRW<[P5600WriteMSAShortLogic], (instregex "^FILL_F(D|W)_PSEUDO$")>;
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def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSERT_F(D|W)_PSEUDO$")>;
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// fexp2_w, fexp2_d
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def : InstRW<[P5600WriteFPUS], (instregex "^FEXP2_(W|D)$")>;
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