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https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 13:11:39 +01:00
[RISCV] Remove unneeded StringRef to std::string conversions in RISCVCompressInstEmitter. NFC
Stop concatenating std::string before streaming into a raw_ostream. Just stream the pieces. Remove some new lines from asserts. Remove std::string concatenation from an assert. assert strings aren't really evaluated like this at runtime. An assertion failure will just print exactly what's between the parentheses in the source.
This commit is contained in:
Craig Topper
parent
d994c519b3
commit
7313f78444
@ -138,13 +138,12 @@ public:
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} // End anonymous namespace.
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bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) {
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assert(Reg->isSubClassOf("Register") && "Reg record should be a Register\n");
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assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be"
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" a RegisterClass\n");
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assert(Reg->isSubClassOf("Register") && "Reg record should be a Register");
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assert(RegClass->isSubClassOf("RegisterClass") &&
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"RegClass record should be a RegisterClass");
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const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass);
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const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
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assert((R != nullptr) &&
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("Register" + Reg->getName().str() + " not defined!!\n").c_str());
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assert((R != nullptr) && "Register not defined!!");
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return RC.contains(R);
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}
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@ -237,9 +236,9 @@ void RISCVCompressInstEmitter::addDagOperandMapping(
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if (Inst.Operands[i].Rec->isSubClassOf("RegisterClass"))
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PrintFatalError(
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Rec->getLoc(),
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("Error in Dag '" + Dag->getAsString() + "' Found immediate: '" +
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II->getAsString() +
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"' but corresponding instruction operand expected a register!"));
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"Error in Dag '" + Dag->getAsString() + "' Found immediate: '" +
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II->getAsString() +
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"' but corresponding instruction operand expected a register!");
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// No pattern validation check possible for values of fixed immediate.
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OperandMap[i].Kind = OpData::Imm;
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OperandMap[i].Data.Imm = II->getValue();
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@ -526,7 +525,8 @@ static unsigned getPredicates(DenseMap<const Record *, unsigned> &PredicateMap,
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}
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PrintFatalError(Rec->getLoc(), "No " + Name +
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" predicate on this operand at all: '" + Rec->getName().str() + "'");
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" predicate on this operand at all: '" +
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Rec->getName() + "'");
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return 0;
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}
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@ -535,7 +535,7 @@ static void printPredicates(std::vector<const Record *> &Predicates,
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for (unsigned i = 0; i < Predicates.size(); ++i) {
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StringRef Pred = Predicates[i]->getValueAsString(Name);
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o << " case " << i + 1 << ": {\n"
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<< " // " << Predicates[i]->getName().str() << "\n"
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<< " // " << Predicates[i]->getName() << "\n"
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<< " " << Pred.data() << "\n"
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<< " }\n";
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}
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@ -572,16 +572,13 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
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// transformed to a C_ADD or a C_MV. When emitting 'uncompress()' function the
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// source and destination are flipped and the sort key needs to change
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// accordingly.
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llvm::stable_sort(CompressPatterns,
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[EType](const CompressPat &LHS, const CompressPat &RHS) {
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if (EType == EmitterType::Compress ||
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EType == EmitterType::CheckCompress)
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return (LHS.Source.TheDef->getName().str() <
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RHS.Source.TheDef->getName().str());
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else
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return (LHS.Dest.TheDef->getName().str() <
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RHS.Dest.TheDef->getName().str());
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});
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llvm::stable_sort(CompressPatterns, [EType](const CompressPat &LHS,
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const CompressPat &RHS) {
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if (EType == EmitterType::Compress || EType == EmitterType::CheckCompress)
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return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName());
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else
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return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName());
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});
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// A list of MCOperandPredicates for all operands in use, and the reverse map.
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std::vector<const Record *> MCOpPredicates;
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@ -685,9 +682,9 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
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// Emit checks for all required features.
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for (auto &Op : FeaturesSet) {
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StringRef Not = Op.first ? "!" : "";
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CondStream.indent(6)
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<< Not << ("STI.getFeatureBits()[" + Namespace + "::" + Op.second + "]").str() +
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" &&\n";
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CondStream.indent(6) << Not << "STI.getFeatureBits()[" << Namespace
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<< "::" << Op.second << "]"
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<< " &&\n";
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}
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// Emit checks for all required feature groups.
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@ -696,8 +693,8 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
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for (auto &Op : Set) {
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bool isLast = &Op == &*Set.rbegin();
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StringRef Not = Op.first ? "!" : "";
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CondStream << Not << ("STI.getFeatureBits()[" + Namespace + "::" + Op.second +
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"]").str();
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CondStream << Not << "STI.getFeatureBits()[" << Namespace
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<< "::" << Op.second << "]";
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if (!isLast)
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CondStream << " || ";
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}
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@ -710,10 +707,8 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
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if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
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if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
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CondStream.indent(6)
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<< "(MI.getOperand("
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<< std::to_string(OpNo) + ").getReg() == MI.getOperand("
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<< std::to_string(SourceOperandMap[OpNo].TiedOpIdx)
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<< ").getReg()) &&\n";
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<< "(MI.getOperand(" << OpNo << ").getReg() == MI.getOperand("
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<< SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n";
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else
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PrintFatalError("Unexpected tied operand types!\n");
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}
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@ -724,27 +719,26 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
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break;
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case OpData::Imm:
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CondStream.indent(6)
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<< "(MI.getOperand(" + std::to_string(OpNo) + ").isImm()) &&\n" +
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" (MI.getOperand(" + std::to_string(OpNo) +
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").getImm() == " +
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std::to_string(SourceOperandMap[OpNo].Data.Imm) + ") &&\n";
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<< "(MI.getOperand(" << OpNo << ").isImm()) &&\n"
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<< " (MI.getOperand(" << OpNo
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<< ").getImm() == " << SourceOperandMap[OpNo].Data.Imm << ") &&\n";
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break;
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case OpData::Reg: {
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Record *Reg = SourceOperandMap[OpNo].Data.Reg;
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CondStream.indent(6) << "(MI.getOperand(" + std::to_string(OpNo) +
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").getReg() == " + Namespace +
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"::" + Reg->getName().str() + ") &&\n";
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CondStream.indent(6)
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<< "(MI.getOperand(" << OpNo << ").getReg() == " << Namespace
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<< "::" << Reg->getName() << ") &&\n";
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break;
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}
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}
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}
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CodeStream.indent(6) << "// " + Dest.AsmString + "\n";
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CodeStream.indent(6) << "// " << Dest.AsmString << "\n";
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if (CompressOrUncompress)
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CodeStream.indent(6) << "OutInst.setOpcode(" + Namespace +
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"::" + Dest.TheDef->getName().str() + ");\n";
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CodeStream.indent(6) << "OutInst.setOpcode(" << Namespace
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<< "::" << Dest.TheDef->getName() << ");\n";
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OpNo = 0;
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for (const auto &DestOperand : Dest.Operands) {
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CodeStream.indent(6) << "// Operand: " + DestOperand.Name + "\n";
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CodeStream.indent(6) << "// Operand: " << DestOperand.Name << "\n";
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switch (DestOperandMap[OpNo].Kind) {
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case OpData::Operand: {
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unsigned OpIdx = DestOperandMap[OpNo].Data.Operand;
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@ -756,37 +750,34 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
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// Don't check register class if this is a tied operand, it was done
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// for the operand its tied to.
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if (DestOperand.getTiedRegister() == -1)
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CondStream.indent(6)
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<< "(MRI.getRegClass(" + Namespace +
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"::" + DestOperand.Rec->getName().str() +
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"RegClassID).contains(" + "MI.getOperand(" +
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std::to_string(OpIdx) + ").getReg())) &&\n";
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CondStream.indent(6) << "(MRI.getRegClass(" << Namespace
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<< "::" << DestOperand.Rec->getName()
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<< "RegClassID).contains(MI.getOperand("
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<< OpIdx << ").getReg())) &&\n";
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if (CompressOrUncompress)
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CodeStream.indent(6) << "OutInst.addOperand(MI.getOperand(" +
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std::to_string(OpIdx) + "));\n";
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CodeStream.indent(6)
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<< "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
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} else {
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// Handling immediate operands.
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if (CompressOrUncompress) {
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unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
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DestOperand.Rec, StringRef("MCOperandPredicate"));
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CondStream.indent(6) << Namespace + "ValidateMCOperand(" +
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"MI.getOperand(" + std::to_string(OpIdx) +
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"), STI, " + std::to_string(Entry) +
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") &&\n";
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CondStream.indent(6)
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<< Namespace << "ValidateMCOperand("
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<< "MI.getOperand(" << OpIdx << "), STI, " << Entry << ") &&\n";
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} else {
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unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
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DestOperand.Rec, StringRef("ImmediateCode"));
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CondStream.indent(6) << "MI.getOperand(" + std::to_string(OpIdx) +
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").isImm() &&\n";
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CondStream.indent(6) << Namespace + "ValidateMachineOperand(" +
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"MI.getOperand(" + std::to_string(OpIdx) +
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"), Subtarget, " + std::to_string(Entry) +
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") &&\n";
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CondStream.indent(6)
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<< "MI.getOperand(" << OpIdx << ").isImm() &&\n";
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CondStream.indent(6) << Namespace << "ValidateMachineOperand("
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<< "MI.getOperand(" << OpIdx
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<< "), Subtarget, " << Entry << ") &&\n";
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}
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if (CompressOrUncompress)
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CodeStream.indent(6) << "OutInst.addOperand(MI.getOperand(" +
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std::to_string(OpIdx) + "));\n";
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CodeStream.indent(6)
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<< "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
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}
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break;
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}
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@ -795,29 +786,29 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
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unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
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DestOperand.Rec, StringRef("MCOperandPredicate"));
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CondStream.indent(6)
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<< Namespace + "ValidateMCOperand(" + "MCOperand::createImm(" +
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std::to_string(DestOperandMap[OpNo].Data.Imm) + "), STI, " +
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std::to_string(Entry) + ") &&\n";
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<< Namespace << "ValidateMCOperand("
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<< "MCOperand::createImm(" << DestOperandMap[OpNo].Data.Imm
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<< "), STI, " << Entry << ") &&\n";
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} else {
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unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
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DestOperand.Rec, StringRef("ImmediateCode"));
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CondStream.indent(6)
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<< Namespace + "ValidateMachineOperand(" + "MachineOperand::CreateImm(" +
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std::to_string(DestOperandMap[OpNo].Data.Imm) + "), SubTarget, " +
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std::to_string(Entry) + ") &&\n";
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<< Namespace
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<< "ValidateMachineOperand(MachineOperand::CreateImm("
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<< DestOperandMap[OpNo].Data.Imm << "), SubTarget, " << Entry
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<< ") &&\n";
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}
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if (CompressOrUncompress)
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CodeStream.indent(6)
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<< "OutInst.addOperand(MCOperand::createImm(" +
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std::to_string(DestOperandMap[OpNo].Data.Imm) + "));\n";
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CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createImm("
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<< DestOperandMap[OpNo].Data.Imm << "));\n";
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} break;
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case OpData::Reg: {
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if (CompressOrUncompress) {
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// Fixed register has been validated at pattern validation time.
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Record *Reg = DestOperandMap[OpNo].Data.Reg;
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CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createReg(" +
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Namespace + "::" + Reg->getName().str() +
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"));\n";
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CodeStream.indent(6)
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<< "OutInst.addOperand(MCOperand::createReg(" << Namespace
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<< "::" << Reg->getName() << "));\n";
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}
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} break;
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}
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@ -830,7 +821,7 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
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}
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Func << CaseStream.str() << "\n";
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// Close brace for the last case.
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Func.indent(4) << "} // case " + CurOp + "\n";
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Func.indent(4) << "} // case " << CurOp << "\n";
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Func.indent(2) << "} // switch\n";
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Func.indent(2) << "return false;\n}\n";
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