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[X86] Separate CDQ and CDQE in the scheduler model.

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According to Agner's data, CDQE is closer to CWDE.

llvm-svn: 329354
This commit is contained in:
Craig Topper 2018-04-05 21:56:19 +00:00
parent c7309ec209
commit 731a02af04
6 changed files with 16 additions and 26 deletions
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6
lib/Target/X86/X86SchedBroadwell.td
View File

@ -455,6 +455,7 @@ def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri", def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
"ADC(16|32|64)i", "ADC(16|32|64)i",
"ADC(8|16|32|64)rr", "ADC(8|16|32|64)rr",
@ -468,9 +469,7 @@ def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
"BTR(16|32|64)rr", "BTR(16|32|64)rr",
"BTS(16|32|64)ri8", "BTS(16|32|64)ri8",
"BTS(16|32|64)rr", "BTS(16|32|64)rr",
"CDQ",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
"CQO",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1", "JMP_1",
@ -605,14 +604,13 @@ def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[BWWriteResGroup9], (instrs CWDE)>; def: InstRW<[BWWriteResGroup9], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri", def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr", "ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i", "ADD(8|16|32|64)i",
"AND(8|16|32|64)ri", "AND(8|16|32|64)ri",
"AND(8|16|32|64)rr", "AND(8|16|32|64)rr",
"AND(8|16|32|64)i", "AND(8|16|32|64)i",
"CBW",
"CLC", "CLC",
"CMC", "CMC",
"CMP(8|16|32|64)ri", "CMP(8|16|32|64)ri",

6
lib/Target/X86/X86SchedHaswell.td
View File

@ -813,6 +813,7 @@ def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;
def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8", def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr", "BT(16|32|64)rr",
"BTC(16|32|64)ri8", "BTC(16|32|64)ri8",
@ -821,8 +822,6 @@ def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8",
"BTR(16|32|64)rr", "BTR(16|32|64)rr",
"BTS(16|32|64)ri8", "BTS(16|32|64)ri8",
"BTS(16|32|64)rr", "BTS(16|32|64)rr",
"CDQ",
"CQO",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1", "JMP_1",
@ -954,14 +953,13 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[HWWriteResGroup10], (instrs CWDE)>; def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)ri", def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr", "ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i", "ADD(8|16|32|64)i",
"AND(8|16|32|64)ri", "AND(8|16|32|64)ri",
"AND(8|16|32|64)rr", "AND(8|16|32|64)rr",
"AND(8|16|32|64)i", "AND(8|16|32|64)i",
"CBW",
"CLC", "CLC",
"CMC", "CMC",
"CMP(8|16|32|64)ri", "CMP(8|16|32|64)ri",

6
lib/Target/X86/X86SchedSandyBridge.td
View File

@ -369,6 +369,7 @@ def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8", def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr", "BT(16|32|64)rr",
"BTC(16|32|64)ri8", "BTC(16|32|64)ri8",
@ -377,8 +378,6 @@ def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"BTR(16|32|64)rr", "BTR(16|32|64)rr",
"BTS(16|32|64)ri8", "BTS(16|32|64)ri8",
"BTS(16|32|64)rr", "BTS(16|32|64)rr",
"CDQ",
"CQO",
"LAHF", "LAHF",
"SAHF", "SAHF",
"SAR(8|16|32|64)ri", "SAR(8|16|32|64)ri",
@ -488,14 +487,13 @@ def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SBWriteResGroup6], (instrs CWDE)>; def: InstRW<[SBWriteResGroup6], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)ri", def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr", "ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i", "ADD(8|16|32|64)i",
"AND(8|16|32|64)ri", "AND(8|16|32|64)ri",
"AND(8|16|32|64)rr", "AND(8|16|32|64)rr",
"AND(8|16|32|64)i", "AND(8|16|32|64)i",
"CBW",
"CMC", "CMC",
"CMP(8|16|32|64)ri", "CMP(8|16|32|64)ri",
"CMP(8|16|32|64)rr", "CMP(8|16|32|64)rr",

6
lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -519,6 +519,7 @@ def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO)>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri", def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
"ADC(16|32|64)i", "ADC(16|32|64)i",
"ADC(8|16|32|64)rr", "ADC(8|16|32|64)rr",
@ -532,10 +533,8 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
"BTR(16|32|64)rr", "BTR(16|32|64)rr",
"BTS(16|32|64)ri8", "BTS(16|32|64)ri8",
"BTS(16|32|64)rr", "BTS(16|32|64)rr",
"CDQ",
"CLAC", "CLAC",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
"CQO",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1", "JMP_1",
@ -609,14 +608,13 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKLWriteResGroup10], (instrs CWDE)>; def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri", def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr", "ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i", "ADD(8|16|32|64)i",
"AND(8|16|32|64)ri", "AND(8|16|32|64)ri",
"AND(8|16|32|64)rr", "AND(8|16|32|64)rr",
"AND(8|16|32|64)i", "AND(8|16|32|64)i",
"CBW",
"CLC", "CLC",
"CMC", "CMC",
"CMP(8|16|32|64)ri", "CMP(8|16|32|64)ri",

6
lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -995,6 +995,7 @@ def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO)>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri", def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri",
"ADC(16|32|64)i", "ADC(16|32|64)i",
"ADC(8|16|32|64)rr", "ADC(8|16|32|64)rr",
@ -1008,10 +1009,8 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri",
"BTR(16|32|64)rr", "BTR(16|32|64)rr",
"BTS(16|32|64)ri8", "BTS(16|32|64)ri8",
"BTS(16|32|64)rr", "BTS(16|32|64)rr",
"CDQ",
"CLAC", "CLAC",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
"CQO",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1", "JMP_1",
@ -1269,14 +1268,13 @@ def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKXWriteResGroup10], (instrs CWDE)>; def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)ri", def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr", "ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i", "ADD(8|16|32|64)i",
"AND(8|16|32|64)ri", "AND(8|16|32|64)ri",
"AND(8|16|32|64)rr", "AND(8|16|32|64)rr",
"AND(8|16|32|64)i", "AND(8|16|32|64)i",
"CBW",
"CLC", "CLC",
"CMC", "CMC",
"CMP(8|16|32|64)ri", "CMP(8|16|32|64)ri",

12
test/CodeGen/X86/schedule-x86_64.ll
View File

@ -3343,7 +3343,7 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_cwde() optsize {
; GENERIC-NEXT: #APP ; GENERIC-NEXT: #APP
; GENERIC-NEXT: cbtw # sched: [1:0.33] ; GENERIC-NEXT: cbtw # sched: [1:0.33]
; GENERIC-NEXT: cltd # sched: [1:0.50] ; GENERIC-NEXT: cltd # sched: [1:0.50]
; GENERIC-NEXT: cltq # sched: [1:0.50] ; GENERIC-NEXT: cltq # sched: [1:0.33]
; GENERIC-NEXT: cqto # sched: [1:0.50] ; GENERIC-NEXT: cqto # sched: [1:0.50]
; GENERIC-NEXT: cwtd # sched: [2:1.00] ; GENERIC-NEXT: cwtd # sched: [2:1.00]
; GENERIC-NEXT: cwtl # sched: [1:0.33] ; GENERIC-NEXT: cwtl # sched: [1:0.33]
@ -3379,7 +3379,7 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_cwde() optsize {
; SANDY-NEXT: #APP ; SANDY-NEXT: #APP
; SANDY-NEXT: cbtw # sched: [1:0.33] ; SANDY-NEXT: cbtw # sched: [1:0.33]
; SANDY-NEXT: cltd # sched: [1:0.50] ; SANDY-NEXT: cltd # sched: [1:0.50]
; SANDY-NEXT: cltq # sched: [1:0.50] ; SANDY-NEXT: cltq # sched: [1:0.33]
; SANDY-NEXT: cqto # sched: [1:0.50] ; SANDY-NEXT: cqto # sched: [1:0.50]
; SANDY-NEXT: cwtd # sched: [2:1.00] ; SANDY-NEXT: cwtd # sched: [2:1.00]
; SANDY-NEXT: cwtl # sched: [1:0.33] ; SANDY-NEXT: cwtl # sched: [1:0.33]
@ -3391,7 +3391,7 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_cwde() optsize {
; HASWELL-NEXT: #APP ; HASWELL-NEXT: #APP
; HASWELL-NEXT: cbtw # sched: [1:0.25] ; HASWELL-NEXT: cbtw # sched: [1:0.25]
; HASWELL-NEXT: cltd # sched: [1:0.50] ; HASWELL-NEXT: cltd # sched: [1:0.50]
; HASWELL-NEXT: cltq # sched: [1:0.50] ; HASWELL-NEXT: cltq # sched: [1:0.25]
; HASWELL-NEXT: cqto # sched: [1:0.50] ; HASWELL-NEXT: cqto # sched: [1:0.50]
; HASWELL-NEXT: cwtd # sched: [2:0.50] ; HASWELL-NEXT: cwtd # sched: [2:0.50]
; HASWELL-NEXT: cwtl # sched: [1:0.25] ; HASWELL-NEXT: cwtl # sched: [1:0.25]
@ -3403,7 +3403,7 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_cwde() optsize {
; BROADWELL-NEXT: #APP ; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: cbtw # sched: [1:0.25] ; BROADWELL-NEXT: cbtw # sched: [1:0.25]
; BROADWELL-NEXT: cltd # sched: [1:0.50] ; BROADWELL-NEXT: cltd # sched: [1:0.50]
; BROADWELL-NEXT: cltq # sched: [1:0.50] ; BROADWELL-NEXT: cltq # sched: [1:0.25]
; BROADWELL-NEXT: cqto # sched: [1:0.50] ; BROADWELL-NEXT: cqto # sched: [1:0.50]
; BROADWELL-NEXT: cwtd # sched: [2:0.50] ; BROADWELL-NEXT: cwtd # sched: [2:0.50]
; BROADWELL-NEXT: cwtl # sched: [1:0.25] ; BROADWELL-NEXT: cwtl # sched: [1:0.25]
@ -3415,7 +3415,7 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_cwde() optsize {
; SKYLAKE-NEXT: #APP ; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: cbtw # sched: [1:0.25] ; SKYLAKE-NEXT: cbtw # sched: [1:0.25]
; SKYLAKE-NEXT: cltd # sched: [1:0.50] ; SKYLAKE-NEXT: cltd # sched: [1:0.50]
; SKYLAKE-NEXT: cltq # sched: [1:0.50] ; SKYLAKE-NEXT: cltq # sched: [1:0.25]
; SKYLAKE-NEXT: cqto # sched: [1:0.50] ; SKYLAKE-NEXT: cqto # sched: [1:0.50]
; SKYLAKE-NEXT: cwtd # sched: [2:0.50] ; SKYLAKE-NEXT: cwtd # sched: [2:0.50]
; SKYLAKE-NEXT: cwtl # sched: [1:0.25] ; SKYLAKE-NEXT: cwtl # sched: [1:0.25]
@ -3427,7 +3427,7 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_cwde() optsize {
; SKX-NEXT: #APP ; SKX-NEXT: #APP
; SKX-NEXT: cbtw # sched: [1:0.25] ; SKX-NEXT: cbtw # sched: [1:0.25]
; SKX-NEXT: cltd # sched: [1:0.50] ; SKX-NEXT: cltd # sched: [1:0.50]
; SKX-NEXT: cltq # sched: [1:0.50] ; SKX-NEXT: cltq # sched: [1:0.25]
; SKX-NEXT: cqto # sched: [1:0.50] ; SKX-NEXT: cqto # sched: [1:0.50]
; SKX-NEXT: cwtd # sched: [2:0.50] ; SKX-NEXT: cwtd # sched: [2:0.50]
; SKX-NEXT: cwtl # sched: [1:0.25] ; SKX-NEXT: cwtl # sched: [1:0.25]