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GlobalISel: Port smarter known bits for umin/umax from DAG
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@ -309,13 +309,43 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
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break;
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}
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case TargetOpcode::G_SMIN:
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case TargetOpcode::G_SMAX:
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case TargetOpcode::G_UMIN:
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case TargetOpcode::G_UMAX: {
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case TargetOpcode::G_SMAX: {
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// TODO: Handle clamp pattern with number of sign bits
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computeKnownBitsMin(MI.getOperand(1).getReg(), MI.getOperand(2).getReg(),
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Known, DemandedElts, Depth + 1);
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break;
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}
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case TargetOpcode::G_UMIN: {
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KnownBits KnownRHS;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known,
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DemandedElts, Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS,
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DemandedElts, Depth + 1);
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// UMIN - we know that the result will have the maximum of the
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// known zero leading bits of the inputs.
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unsigned LeadZero = Known.countMinLeadingZeros();
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LeadZero = std::max(LeadZero, KnownRHS.countMinLeadingZeros());
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Known &= KnownRHS;
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Known.Zero.setHighBits(LeadZero);
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break;
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}
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case TargetOpcode::G_UMAX: {
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KnownBits KnownRHS;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known,
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DemandedElts, Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS,
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DemandedElts, Depth + 1);
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// UMAX - we know that the result will have the maximum of the
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// known one leading bits of the inputs.
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unsigned LeadOne = Known.countMinLeadingOnes();
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LeadOne = std::max(LeadOne, KnownRHS.countMinLeadingOnes());
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Known.Zero &= KnownRHS.Zero;
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Known.One &= KnownRHS.One;
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Known.One.setHighBits(LeadOne);
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break;
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}
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case TargetOpcode::G_FCMP:
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case TargetOpcode::G_ICMP: {
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if (TL.getBooleanContents(DstTy.isVector(),
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@ -265,3 +265,52 @@ body: |
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$vgpr0 = COPY %and
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...
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# We can conclude the number of bits based only on one operand
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---
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name: remove_and_umin_lhs_only
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
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; CHECK-LABEL: name: remove_and_umin_lhs_only
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; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
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; CHECK: %val:_(s32) = COPY $vgpr4
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; CHECK: %k255:_(s32) = G_CONSTANT i32 255
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; CHECK: %umin0:_(s32) = G_UMIN %val, %k255
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; CHECK: $vgpr0 = COPY %umin0(s32)
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%ptr0:_(p1) = COPY $vgpr0_vgpr1
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%ptr1:_(p1) = COPY $vgpr2_vgpr3
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%val:_(s32) = COPY $vgpr4
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%k255:_(s32) = G_CONSTANT i32 255
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%umin0:_(s32) = G_UMIN %val, %k255
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%and:_(s32) = G_AND %umin0, %k255
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$vgpr0 = COPY %and
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...
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---
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name: remove_and_umin_rhs_only
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
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; CHECK-LABEL: name: remove_and_umin_rhs_only
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; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
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; CHECK: %val:_(s32) = COPY $vgpr4
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; CHECK: %k255:_(s32) = G_CONSTANT i32 255
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; CHECK: %umin0:_(s32) = G_UMIN %k255, %val
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; CHECK: $vgpr0 = COPY %umin0(s32)
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%ptr0:_(p1) = COPY $vgpr0_vgpr1
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%ptr1:_(p1) = COPY $vgpr2_vgpr3
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%val:_(s32) = COPY $vgpr4
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%k255:_(s32) = G_CONSTANT i32 255
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%umin0:_(s32) = G_UMIN %k255, %val
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%and:_(s32) = G_AND %umin0, %k255
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$vgpr0 = COPY %and
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...
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@ -701,3 +701,27 @@ TEST_F(AArch64GISelMITest, TestKnownBitsBSwapBitReverse) {
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EXPECT_EQ(TestVal, BitReverseKnown.One.getZExtValue());
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EXPECT_EQ(~TestVal, BitReverseKnown.Zero.getZExtValue());
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}
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TEST_F(AArch64GISelMITest, TestKnownBitsUMax) {
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StringRef MIRString = R"(
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%val:_(s32) = COPY $w0
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%zext:_(s64) = G_ZEXT %val
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%const:_(s64) = G_CONSTANT i64 -256
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%umax:_(s64) = G_UMAX %zext, %const
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%copy_umax:_(s64) = COPY %umax
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)";
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setUp(MIRString);
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if (!TM)
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return;
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Register CopyUMax = Copies[Copies.size() - 1];
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GISelKnownBits Info(*MF);
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KnownBits KnownUmax = Info.getKnownBits(CopyUMax);
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EXPECT_EQ(64u, KnownUmax.getBitWidth());
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EXPECT_EQ(0u, KnownUmax.Zero.getZExtValue());
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EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
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EXPECT_EQ(0u, KnownUmax.Zero.getZExtValue());
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EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
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}
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