mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 02:52:53 +02:00
[Hexagon] Update timing classes
llvm-svn: 348183
This commit is contained in:
Krzysztof Parzyszek
parent
a50481fbda
commit
736a301e6b
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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@ -1,4 +1,4 @@
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//===- HexagonDepTimingClasses.h ------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -10,7 +10,6 @@
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
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#define TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
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@ -20,19 +19,22 @@ namespace llvm {
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inline bool is_TC3x(unsigned SchedClass) {
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switch (SchedClass) {
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case Hexagon::Sched::tc_16d0d8d5:
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case Hexagon::Sched::tc_1853ea6d:
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case Hexagon::Sched::tc_60571023:
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case Hexagon::Sched::tc_7934b9df:
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case Hexagon::Sched::tc_8fd5f294:
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case Hexagon::Sched::tc_b9c0b731:
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case Hexagon::Sched::tc_bcc96cee:
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case Hexagon::Sched::tc_c6ce9b3f:
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case Hexagon::Sched::tc_c6ebf8dd:
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case Hexagon::Sched::tc_c82dc1ff:
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case Hexagon::Sched::tc_caaebcba:
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case Hexagon::Sched::tc_cf59f215:
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case Hexagon::Sched::tc_e913dc32:
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case Hexagon::Sched::tc_05d3a09b:
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case Hexagon::Sched::tc_0d8f5752:
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case Hexagon::Sched::tc_13bfbcf9:
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case Hexagon::Sched::tc_174516e8:
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case Hexagon::Sched::tc_1a2fd869:
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case Hexagon::Sched::tc_5b54b33f:
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case Hexagon::Sched::tc_6b25e783:
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case Hexagon::Sched::tc_76851da1:
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case Hexagon::Sched::tc_9debc299:
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case Hexagon::Sched::tc_a9d88b22:
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case Hexagon::Sched::tc_bafaade3:
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case Hexagon::Sched::tc_bcf98408:
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case Hexagon::Sched::tc_c8ce0b5c:
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case Hexagon::Sched::tc_d1aa9eaa:
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case Hexagon::Sched::tc_d773585a:
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case Hexagon::Sched::tc_df3319ed:
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return true;
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default:
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return false;
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@ -41,8 +43,8 @@ inline bool is_TC3x(unsigned SchedClass) {
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inline bool is_TC2early(unsigned SchedClass) {
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switch (SchedClass) {
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case Hexagon::Sched::tc_14cd4cfa:
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case Hexagon::Sched::tc_2a160009:
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case Hexagon::Sched::tc_b4407292:
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case Hexagon::Sched::tc_fc3999b4:
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return true;
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default:
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return false;
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@ -51,12 +53,12 @@ inline bool is_TC2early(unsigned SchedClass) {
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inline bool is_TC4x(unsigned SchedClass) {
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switch (SchedClass) {
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case Hexagon::Sched::tc_038a1342:
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case Hexagon::Sched::tc_4d99bca9:
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case Hexagon::Sched::tc_6792d5ff:
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case Hexagon::Sched::tc_9c00ce8d:
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case Hexagon::Sched::tc_d580173f:
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case Hexagon::Sched::tc_f3eaa14b:
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case Hexagon::Sched::tc_2ff964b4:
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case Hexagon::Sched::tc_3a867367:
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case Hexagon::Sched::tc_3b470976:
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case Hexagon::Sched::tc_4560740b:
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case Hexagon::Sched::tc_a58fd5cc:
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case Hexagon::Sched::tc_b8bffe55:
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return true;
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default:
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return false;
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@ -65,23 +67,23 @@ inline bool is_TC4x(unsigned SchedClass) {
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inline bool is_TC2(unsigned SchedClass) {
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switch (SchedClass) {
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case Hexagon::Sched::tc_00afc57e:
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case Hexagon::Sched::tc_1b9c9ee5:
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case Hexagon::Sched::tc_234a11a5:
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case Hexagon::Sched::tc_2b6f77c6:
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case Hexagon::Sched::tc_41d5298e:
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case Hexagon::Sched::tc_5ba5997d:
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case Hexagon::Sched::tc_84df2cd3:
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case Hexagon::Sched::tc_87735c3b:
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case Hexagon::Sched::tc_897d1a9d:
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case Hexagon::Sched::tc_976ddc4f:
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case Hexagon::Sched::tc_b44c6e2a:
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case Hexagon::Sched::tc_b9c4623f:
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case Hexagon::Sched::tc_c2f7d806:
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case Hexagon::Sched::tc_c74f796f:
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case Hexagon::Sched::tc_d088982c:
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case Hexagon::Sched::tc_ef84f62f:
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case Hexagon::Sched::tc_f49e76f4:
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case Hexagon::Sched::tc_002cb246:
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case Hexagon::Sched::tc_14b5c689:
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case Hexagon::Sched::tc_4414d8b1:
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case Hexagon::Sched::tc_61830035:
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case Hexagon::Sched::tc_679309b8:
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case Hexagon::Sched::tc_703e822c:
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case Hexagon::Sched::tc_779080bf:
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case Hexagon::Sched::tc_784490da:
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case Hexagon::Sched::tc_88b4f13d:
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case Hexagon::Sched::tc_9461ff31:
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case Hexagon::Sched::tc_9e313203:
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case Hexagon::Sched::tc_a813cf9a:
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case Hexagon::Sched::tc_bfec0f01:
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case Hexagon::Sched::tc_cf8126ae:
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case Hexagon::Sched::tc_f429765c:
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case Hexagon::Sched::tc_f675fee8:
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case Hexagon::Sched::tc_f9058dd7:
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return true;
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default:
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return false;
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@ -90,45 +92,45 @@ inline bool is_TC2(unsigned SchedClass) {
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inline bool is_TC1(unsigned SchedClass) {
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switch (SchedClass) {
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case Hexagon::Sched::tc_181af5d0:
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case Hexagon::Sched::tc_1b82a277:
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case Hexagon::Sched::tc_1e856f58:
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case Hexagon::Sched::tc_351fed2d:
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case Hexagon::Sched::tc_3669266a:
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case Hexagon::Sched::tc_3cb8ea06:
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case Hexagon::Sched::tc_452f85af:
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case Hexagon::Sched::tc_481e5e5c:
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case Hexagon::Sched::tc_49eb22c8:
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case Hexagon::Sched::tc_523fcf30:
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case Hexagon::Sched::tc_52d7bbea:
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case Hexagon::Sched::tc_53bc8a6a:
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case Hexagon::Sched::tc_540fdfbc:
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case Hexagon::Sched::tc_55050d58:
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case Hexagon::Sched::tc_609d2efe:
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case Hexagon::Sched::tc_68cb12ce:
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case Hexagon::Sched::tc_6ebb4a12:
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case Hexagon::Sched::tc_6efc556e:
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case Hexagon::Sched::tc_73043bf4:
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case Hexagon::Sched::tc_7a830544:
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case Hexagon::Sched::tc_855b0b61:
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case Hexagon::Sched::tc_8fe6b782:
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case Hexagon::Sched::tc_90f3e30c:
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case Hexagon::Sched::tc_97743097:
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case Hexagon::Sched::tc_99be14ca:
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case Hexagon::Sched::tc_9faf76ae:
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case Hexagon::Sched::tc_a46f0df5:
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case Hexagon::Sched::tc_a904d137:
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case Hexagon::Sched::tc_b9488031:
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case Hexagon::Sched::tc_be706f30:
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case Hexagon::Sched::tc_c6aa82f7:
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case Hexagon::Sched::tc_cde8b071:
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case Hexagon::Sched::tc_d6bf0472:
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case Hexagon::Sched::tc_dbdffe3d:
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case Hexagon::Sched::tc_e0739b8c:
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case Hexagon::Sched::tc_e1e99bfa:
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case Hexagon::Sched::tc_e9fae2d6:
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case Hexagon::Sched::tc_f2704b9a:
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case Hexagon::Sched::tc_f8eeed7a:
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case Hexagon::Sched::tc_0663f615:
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case Hexagon::Sched::tc_0a705168:
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case Hexagon::Sched::tc_0ae0825c:
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case Hexagon::Sched::tc_1b6f7cec:
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case Hexagon::Sched::tc_1fc97744:
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case Hexagon::Sched::tc_20cdee80:
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case Hexagon::Sched::tc_2332b92e:
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case Hexagon::Sched::tc_2eabeebe:
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case Hexagon::Sched::tc_3a2ec948:
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case Hexagon::Sched::tc_3d495a39:
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case Hexagon::Sched::tc_4c5ba658:
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case Hexagon::Sched::tc_56336eb0:
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case Hexagon::Sched::tc_56f114f4:
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case Hexagon::Sched::tc_57890846:
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case Hexagon::Sched::tc_5a2711e5:
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case Hexagon::Sched::tc_5b7c0967:
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case Hexagon::Sched::tc_640086b5:
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case Hexagon::Sched::tc_643b4717:
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case Hexagon::Sched::tc_85c9c08f:
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case Hexagon::Sched::tc_85d5d03f:
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case Hexagon::Sched::tc_862b3e70:
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case Hexagon::Sched::tc_946df596:
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case Hexagon::Sched::tc_9c3ecd83:
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case Hexagon::Sched::tc_9fc3dae0:
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case Hexagon::Sched::tc_a1123dda:
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case Hexagon::Sched::tc_a1c00888:
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case Hexagon::Sched::tc_ae53734a:
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case Hexagon::Sched::tc_b31c2e97:
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case Hexagon::Sched::tc_b4b5c03a:
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case Hexagon::Sched::tc_b51dc29a:
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case Hexagon::Sched::tc_bf41e621:
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case Hexagon::Sched::tc_cd374165:
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case Hexagon::Sched::tc_cfd8378a:
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case Hexagon::Sched::tc_d5b7b0c1:
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case Hexagon::Sched::tc_d9d43ecb:
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case Hexagon::Sched::tc_db2bce9c:
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case Hexagon::Sched::tc_de4df740:
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case Hexagon::Sched::tc_de554571:
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case Hexagon::Sched::tc_e78647bd:
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return true;
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default:
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return false;
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@ -526,11 +526,11 @@ let isCodeGenOnly = 1, isPseudo = 1, Defs = [CS], Uses = [CS],
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addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
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def NAME#_pci : LDInst<(outs RC:$Rd32, IntRegs:$Rx32),
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(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Cs),
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".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_4403ca65>;
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".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_e93a3d71>;
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def NAME#_pcr : LDInst<(outs RC:$Rd32, IntRegs:$Rx32),
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(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Cs),
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".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_2fc0c436>;
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".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_44d3da28>;
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}
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}
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@ -547,11 +547,11 @@ let isCodeGenOnly = 1, isPseudo = 1, Defs = [CS], Uses = [CS],
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addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
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def NAME#_pci : STInst<(outs IntRegs:$Rx32),
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(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
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".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_9fdb5406>;
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".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_327843a7>;
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def NAME#_pcr : STInst<(outs IntRegs:$Rx32),
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(ins IntRegs:$Rx32in, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
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".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_f86c328a>;
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".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_c4f596e3>;
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}
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}
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