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[Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trap
The trap instruction is intercepted by various runtime environments, and instead of a crash it creates confusion. This reapplies r354606 with a fix. llvm-svn: 354611
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@ -1313,6 +1313,38 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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return true;
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}
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case Hexagon::PS_crash: {
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// Generate a misaligned load that is guaranteed to cause a crash.
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class CrashPseudoSourceValue : public PseudoSourceValue {
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public:
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CrashPseudoSourceValue(const TargetInstrInfo &TII)
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: PseudoSourceValue(TargetCustom, TII) {}
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bool isConstant(const MachineFrameInfo *) const override {
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return false;
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}
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bool isAliased(const MachineFrameInfo *) const override {
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return false;
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}
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bool mayAlias(const MachineFrameInfo *) const override {
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return false;
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}
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void printCustom(raw_ostream &OS) const override {
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OS << "MisalignedCrash";
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}
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};
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static const CrashPseudoSourceValue CrashPSV(*this);
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo(&CrashPSV),
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MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 8, 1);
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BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
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.addImm(0xBADC0FEE) // Misaligned load.
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.addMemOperand(MMO);
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MBB.erase(MI);
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return true;
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}
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case Hexagon::PS_tailcall_i:
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MI.setDesc(get(Hexagon::J2_jump));
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return true;
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@ -3081,7 +3081,7 @@ def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)),
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def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
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def: Pat<(HexagonBARRIER), (Y2_barrier)>;
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def: Pat<(trap), (J2_trap0 (i32 0))>;
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def: Pat<(trap), (PS_crash)>;
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// Read cycle counter.
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def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
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@ -559,3 +559,8 @@ defm PS_storerh : NewCircularStore<IntRegs, HalfWordAccess>;
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defm PS_storerf : NewCircularStore<IntRegs, HalfWordAccess>;
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defm PS_storeri : NewCircularStore<IntRegs, WordAccess>;
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defm PS_storerd : NewCircularStore<DoubleRegs, WordAccess>;
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// A pseudo that generates a runtime crash. This is used to implement
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// __builtin_trap.
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let hasSideEffects = 1, isPseudo = 1, isCodeGenOnly = 1, isSolo = 1 in
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def PS_crash: InstHexagon<(outs), (ins), "", [], "", PSEUDO, TypePSEUDO>;
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20
test/CodeGen/Hexagon/trap-crash.ll
Normal file
20
test/CodeGen/Hexagon/trap-crash.ll
Normal file
@ -0,0 +1,20 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Generate code that is guaranteed to crash. At the moment, it's a
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; misaligned load.
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; CHECK: memd(##3134984174)
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target triple = "hexagon"
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; Function Attrs: noreturn nounwind
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define i32 @f0() #0 {
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entry:
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tail call void @llvm.trap()
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unreachable
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}
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; Function Attrs: cold noreturn nounwind
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declare void @llvm.trap() #1
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attributes #0 = { noreturn nounwind "target-cpu"="hexagonv60" }
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attributes #1 = { cold noreturn nounwind }
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@ -1,5 +1,7 @@
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; RUN: llc -march=hexagon -trap-unreachable < %s | FileCheck %s
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; CHECK: trap
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; Trap is implemented via a misaligned load.
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; CHECK: memd(##3134984174)
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define void @fred() #0 {
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unreachable
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