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https://github.com/RPCS3/llvm-mirror.git
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[EarlyIfConversion] Avoid producing selects with identical operands
This extends the early-ifcvt pass to avoid a few more cases where the resulting select instructions would have matching operands. Additionally, we now use TII to determine "sameness" of the operands so that as TII gets smarter, so too will ifcvt. The attached test case was bugpoint-reduced down from CINT2000/252.eon in the test-suite. See: https://clang.godbolt.org/z/WvnrcrGEn Differential Revision: https://reviews.llvm.org/D101508
This commit is contained in:
Jon Roelofs
parent
0386626f22
commit
738d110269
@ -557,6 +557,52 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB, bool Predicate) {
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return true;
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}
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/// \return true iff the two registers are known to have the same value.
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static bool hasSameValue(const MachineRegisterInfo &MRI,
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const TargetInstrInfo *TII, Register TReg,
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Register FReg) {
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if (TReg == FReg)
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return true;
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if (!TReg.isVirtual() || !FReg.isVirtual())
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return false;
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const MachineInstr *TDef = MRI.getUniqueVRegDef(TReg);
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const MachineInstr *FDef = MRI.getUniqueVRegDef(FReg);
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if (!TDef || !FDef)
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return false;
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// If there are side-effects, all bets are off.
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if (TDef->hasUnmodeledSideEffects())
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return false;
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// If the instruction could modify memory, or there may be some intervening
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// store between the two, we can't consider them to be equal.
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if (TDef->mayLoadOrStore() && !TDef->isDereferenceableInvariantLoad(nullptr))
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return false;
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// We also can't guarantee that they are the same if, for example, the
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// instructions are both a copy from a physical reg, because some other
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// instruction may have modified the value in that reg between the two
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// defining insts.
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if (any_of(TDef->uses(), [](const MachineOperand &MO) {
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return MO.isReg() && MO.getReg().isPhysical();
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}))
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return false;
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// Check whether the two defining instructions produce the same value(s).
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if (!TII->produceSameValue(*TDef, *FDef, &MRI))
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return false;
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// Further, check that the two defs come from corresponding operands.
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int TIdx = TDef->findRegisterDefOperandIdx(TReg);
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int FIdx = FDef->findRegisterDefOperandIdx(FReg);
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if (TIdx == -1 || FIdx == -1)
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return false;
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return TIdx == FIdx;
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}
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/// replacePHIInstrs - Completely replace PHI instructions with selects.
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/// This is possible when the only Tail predecessors are the if-converted
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/// blocks.
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@ -571,7 +617,15 @@ void SSAIfConv::replacePHIInstrs() {
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PHIInfo &PI = PHIs[i];
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LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
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Register DstReg = PI.PHI->getOperand(0).getReg();
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TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
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if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) {
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// We do not need the select instruction if both incoming values are
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// equal, but we do need a COPY.
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BuildMI(*Head, FirstTerm, HeadDL, TII->get(TargetOpcode::COPY), DstReg)
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.addReg(PI.TReg);
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} else {
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TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg,
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PI.FReg);
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}
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LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
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PI.PHI->eraseFromParent();
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PI.PHI = nullptr;
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@ -592,7 +646,7 @@ void SSAIfConv::rewritePHIOperands() {
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unsigned DstReg = 0;
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LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
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if (PI.TReg == PI.FReg) {
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if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) {
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// We do not need the select instruction if both incoming values are
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// equal.
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DstReg = PI.TReg;
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250
test/CodeGen/AArch64/early-ifcvt-same-value.mir
Normal file
250
test/CodeGen/AArch64/early-ifcvt-same-value.mir
Normal file
@ -0,0 +1,250 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=early-ifcvt -stress-early-ifcvt -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: fmov0
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr32, preferred-register: '' }
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- { id: 1, class: fpr32, preferred-register: '' }
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- { id: 2, class: fpr32, preferred-register: '' }
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- { id: 3, class: fpr32, preferred-register: '' }
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- { id: 4, class: fpr32, preferred-register: '' }
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- { id: 5, class: gpr32common, preferred-register: '' }
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- { id: 6, class: gpr32, preferred-register: '' }
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- { id: 7, class: fpr32, preferred-register: '' }
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- { id: 8, class: fpr32, preferred-register: '' }
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liveins:
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- { reg: '$s1', virtual-reg: '%4' }
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- { reg: '$w0', virtual-reg: '%5' }
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body: |
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; CHECK-LABEL: name: fmov0
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; CHECK: bb.0.entry:
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; CHECK: liveins: $s1, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
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; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: [[FMOVS0_1:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[FMOVS0_]]
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; CHECK: $s0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $s0
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: $s1, $w0
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%5:gpr32common = COPY $w0
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%4:fpr32 = COPY $s1
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%6:gpr32 = SUBSWri %5, 1, 0, implicit-def $nzcv
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Bcc 1, %bb.2, implicit $nzcv
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B %bb.1
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bb.1:
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successors: %bb.3
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%0:fpr32 = FMOVS0
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B %bb.3
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bb.2:
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successors: %bb.3
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%1:fpr32 = FMOVS0
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bb.3:
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%2:fpr32 = PHI %1, %bb.2, %0, %bb.1
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$s0 = COPY %2
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RET_ReallyLR implicit $s0
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...
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---
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name: fmov0_extrapred
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr32, preferred-register: '' }
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- { id: 1, class: fpr32, preferred-register: '' }
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- { id: 2, class: fpr32, preferred-register: '' }
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- { id: 3, class: fpr32, preferred-register: '' }
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- { id: 4, class: fpr32, preferred-register: '' }
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- { id: 5, class: gpr32common, preferred-register: '' }
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- { id: 6, class: gpr32, preferred-register: '' }
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- { id: 7, class: fpr32, preferred-register: '' }
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- { id: 8, class: fpr32, preferred-register: '' }
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liveins:
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- { reg: '$s1', virtual-reg: '%4' }
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- { reg: '$w0', virtual-reg: '%5' }
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body: |
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; CHECK-LABEL: name: fmov0_extrapred
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: liveins: $s1, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
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; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: [[FMOVS0_1:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: B %bb.4
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; CHECK: bb.1:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF
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; CHECK: B %bb.4
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; CHECK: bb.4:
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; CHECK: [[PHI:%[0-9]+]]:fpr32 = PHI [[FMOVS0_]], %bb.0, [[DEF]], %bb.1
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; CHECK: $s0 = COPY [[PHI]]
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; CHECK: RET_ReallyLR implicit $s0
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: $s1, $w0
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%5:gpr32common = COPY $w0
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%4:fpr32 = COPY $s1
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%6:gpr32 = SUBSWri %5, 1, 0, implicit-def $nzcv
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Bcc 1, %bb.2, implicit $nzcv
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B %bb.1
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bb.4:
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successors: %bb.3
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; Make sure we also handle the case when there are extra predecessors on
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; the tail block.
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%3:fpr32 = IMPLICIT_DEF
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B %bb.3
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bb.1:
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successors: %bb.3
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%0:fpr32 = FMOVS0
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B %bb.3
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bb.2:
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successors: %bb.3
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%1:fpr32 = FMOVS0
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bb.3:
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%2:fpr32 = PHI %1, %bb.2, %0, %bb.1, %3, %bb.4
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$s0 = COPY %2
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RET_ReallyLR implicit $s0
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...
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---
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name: copy_physreg
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr32, preferred-register: '' }
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- { id: 1, class: fpr32, preferred-register: '' }
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- { id: 2, class: fpr32, preferred-register: '' }
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- { id: 3, class: fpr32, preferred-register: '' }
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- { id: 4, class: fpr32, preferred-register: '' }
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- { id: 5, class: gpr32common, preferred-register: '' }
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- { id: 6, class: gpr32, preferred-register: '' }
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- { id: 7, class: fpr32, preferred-register: '' }
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- { id: 8, class: fpr32, preferred-register: '' }
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- { id: 9, class: fpr32, preferred-register: '' }
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- { id: 10, class: fpr32, preferred-register: '' }
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liveins:
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- { reg: '$s1', virtual-reg: '%4' }
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- { reg: '$w0', virtual-reg: '%5' }
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body: |
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; CHECK-LABEL: name: copy_physreg
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; CHECK: bb.0.entry:
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; CHECK: liveins: $s1, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
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; CHECK: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF implicit-def $s1
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[DEF1:%[0-9]+]]:fpr32 = IMPLICIT_DEF implicit-def $s1
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; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY2]], [[COPY3]], 1, implicit $nzcv
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; CHECK: $s0 = COPY [[FCSELSrrr]]
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; CHECK: RET_ReallyLR implicit $s0
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: $s1, $w0
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%5:gpr32common = COPY $w0
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%4:fpr32 = COPY $s1
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%6:gpr32 = SUBSWri %5, 1, 0, implicit-def $nzcv
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Bcc 1, %bb.2, implicit $nzcv
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B %bb.1
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bb.1:
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successors: %bb.3
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%9:fpr32 = IMPLICIT_DEF implicit-def $s1
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%0:fpr32 = COPY $s1
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B %bb.3
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bb.2:
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successors: %bb.3
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%10:fpr32 = IMPLICIT_DEF implicit-def $s1
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%1:fpr32 = COPY $s1
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bb.3:
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%2:fpr32 = PHI %1, %bb.2, %0, %bb.1
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$s0 = COPY %2
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RET_ReallyLR implicit $s0
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...
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---
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name: same_def_different_operand
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr32, preferred-register: '' }
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- { id: 1, class: fpr32, preferred-register: '' }
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- { id: 2, class: gpr64common, preferred-register: '' }
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- { id: 3, class: fpr32, preferred-register: '' }
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- { id: 4, class: fpr32, preferred-register: '' }
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- { id: 5, class: gpr32common, preferred-register: '' }
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- { id: 6, class: gpr32, preferred-register: '' }
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- { id: 7, class: fpr32, preferred-register: '' }
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- { id: 8, class: fpr32, preferred-register: '' }
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- { id: 9, class: gpr64common, preferred-register: '' }
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- { id: 10, class: gpr64, preferred-register: '' }
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- { id: 11, class: gpr64common, preferred-register: '' }
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liveins:
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- { reg: '$s1', virtual-reg: '%4' }
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- { reg: '$w0', virtual-reg: '%5' }
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- { reg: '$x2', virtual-reg: '%9' }
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body: |
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; CHECK-LABEL: name: same_def_different_operand
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; CHECK: bb.0.entry:
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; CHECK: liveins: $s1, $w0, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK: early-clobber %11:gpr64common, %10:gpr64 = LDRXpre [[COPY]], 16
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; CHECK: [[COPY1:%[0-9]+]]:gpr32common = COPY $w0
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 1, 0, implicit-def $nzcv
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; CHECK: [[CSELXr:%[0-9]+]]:gpr64common = CSELXr %11, %10, 1, implicit $nzcv
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; CHECK: $x2 = COPY [[CSELXr]]
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; CHECK: RET_ReallyLR implicit $x2
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: $s1, $w0, $x2
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%9:gpr64common = COPY $x0
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early-clobber %11:gpr64common, %10:gpr64 = LDRXpre %9:gpr64common, 16
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%5:gpr32common = COPY $w0
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%4:fpr32 = COPY $s1
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%6:gpr32 = SUBSWri %5, 1, 0, implicit-def $nzcv
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Bcc 1, %bb.2, implicit $nzcv
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B %bb.1
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bb.1:
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successors: %bb.3
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B %bb.3
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bb.2:
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successors: %bb.3
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B %bb.3
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bb.3:
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%2:gpr64common = PHI %11, %bb.2, %10, %bb.1
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$x2 = COPY %2
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RET_ReallyLR implicit $x2
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...
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@ -34,28 +34,27 @@ define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot
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; CHECK-GEN-ISEL-TRUE-NEXT: std r0, 16(r1)
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; CHECK-GEN-ISEL-TRUE-NEXT: stdu r1, -64(r1)
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; CHECK-GEN-ISEL-TRUE-NEXT: mr r30, r3
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; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $x4
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; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $x3
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; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $r29
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; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 4
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; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_1: # %while.cond11
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; CHECK-GEN-ISEL-TRUE-NEXT: #
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; CHECK-GEN-ISEL-TRUE-NEXT: lwz r3, 0(r3)
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; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r3, 0
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; CHECK-GEN-ISEL-TRUE-NEXT: lwz r4, 0(r3)
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; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r4, 0
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; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_3
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; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.2: # %while.body21
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; CHECK-GEN-ISEL-TRUE-NEXT: #
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; CHECK-GEN-ISEL-TRUE-NEXT: bl ZN3pov10pov_callocEmmPKciS1_pov
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; CHECK-GEN-ISEL-TRUE-NEXT: nop
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; CHECK-GEN-ISEL-TRUE-NEXT: addi r4, r29, 1
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; CHECK-GEN-ISEL-TRUE-NEXT: srwi r6, r29, 1
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; CHECK-GEN-ISEL-TRUE-NEXT: srwi r5, r29, 1
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; CHECK-GEN-ISEL-TRUE-NEXT: srawi r4, r4, 1
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; CHECK-GEN-ISEL-TRUE-NEXT: std r3, 0(r3)
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; CHECK-GEN-ISEL-TRUE-NEXT: addze r5, r4
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; CHECK-GEN-ISEL-TRUE-NEXT: mr r4, r3
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; CHECK-GEN-ISEL-TRUE-NEXT: isel r29, r5, r6, 4*cr5+lt
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; CHECK-GEN-ISEL-TRUE-NEXT: addze r4, r4
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; CHECK-GEN-ISEL-TRUE-NEXT: isel r29, r4, r5, 4*cr5+lt
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; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_1
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; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_3: # %lor.rhs
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; CHECK-GEN-ISEL-TRUE-NEXT: std r30, 16(r4)
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; CHECK-GEN-ISEL-TRUE-NEXT: std r30, 16(r3)
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; CHECK-GEN-ISEL-TRUE-NEXT: addi r1, r1, 64
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; CHECK-GEN-ISEL-TRUE-NEXT: ld r0, 16(r1)
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; CHECK-GEN-ISEL-TRUE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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@ -75,37 +74,36 @@ define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot
|
||||
; CHECK-NEXT: std r0, 16(r1)
|
||||
; CHECK-NEXT: stdu r1, -64(r1)
|
||||
; CHECK-NEXT: mr r30, r3
|
||||
; CHECK-NEXT: # implicit-def: $x4
|
||||
; CHECK-NEXT: # implicit-def: $x3
|
||||
; CHECK-NEXT: # implicit-def: $r29
|
||||
; CHECK-NEXT: .p2align 4
|
||||
; CHECK-NEXT: .LBB0_1: # %while.cond11
|
||||
; CHECK-NEXT: #
|
||||
; CHECK-NEXT: lwz r3, 0(r3)
|
||||
; CHECK-NEXT: cmplwi r3, 0
|
||||
; CHECK-NEXT: lwz r4, 0(r3)
|
||||
; CHECK-NEXT: cmplwi r4, 0
|
||||
; CHECK-NEXT: beq cr0, .LBB0_6
|
||||
; CHECK-NEXT: # %bb.2: # %while.body21
|
||||
; CHECK-NEXT: #
|
||||
; CHECK-NEXT: bl ZN3pov10pov_callocEmmPKciS1_pov
|
||||
; CHECK-NEXT: nop
|
||||
; CHECK-NEXT: addi r4, r29, 1
|
||||
; CHECK-NEXT: srwi r6, r29, 1
|
||||
; CHECK-NEXT: srwi r5, r29, 1
|
||||
; CHECK-NEXT: srawi r4, r4, 1
|
||||
; CHECK-NEXT: std r3, 0(r3)
|
||||
; CHECK-NEXT: addze r5, r4
|
||||
; CHECK-NEXT: mr r4, r3
|
||||
; CHECK-NEXT: addze r4, r4
|
||||
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_4
|
||||
; CHECK-NEXT: # %bb.3: # %while.body21
|
||||
; CHECK-NEXT: #
|
||||
; CHECK-NEXT: ori r29, r6, 0
|
||||
; CHECK-NEXT: ori r29, r5, 0
|
||||
; CHECK-NEXT: b .LBB0_5
|
||||
; CHECK-NEXT: .LBB0_4: # %while.body21
|
||||
; CHECK-NEXT: #
|
||||
; CHECK-NEXT: addi r29, r5, 0
|
||||
; CHECK-NEXT: addi r29, r4, 0
|
||||
; CHECK-NEXT: .LBB0_5: # %while.body21
|
||||
; CHECK-NEXT: #
|
||||
; CHECK-NEXT: b .LBB0_1
|
||||
; CHECK-NEXT: .LBB0_6: # %lor.rhs
|
||||
; CHECK-NEXT: std r30, 16(r4)
|
||||
; CHECK-NEXT: std r30, 16(r3)
|
||||
; CHECK-NEXT: addi r1, r1, 64
|
||||
; CHECK-NEXT: ld r0, 16(r1)
|
||||
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
|
||||
|
||||
Loading…
Reference in New Issue
Block a user