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[ARM][MVE] Refactor complex vector intrinsics [NFCI]
Summary: This patch refactors instruction selection of the complex vector addition, multiplication and multiply-add intrinsics, so that it is now based on TableGen patterns rather than C++ code. It also changes the first parameter (halving vs non-halving) of the arm_mve_vcaddq IR intrinsic to match the corresponding instruction encoding, hence it requires some changes in the tests. The patch addresses David's comment in https://reviews.llvm.org/D71190 Reviewers: dmgreen, ostannard, simon_tatham, MarkMurrayARM Reviewed By: dmgreen Subscribers: merge_guards_bot, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D71245
This commit is contained in:
Mikhail Maltsev
parent
000106ed96
commit
73964fed6d
@ -984,7 +984,9 @@ multiclass MVEMXPredicated<list<LLVMType> rets, list<LLVMType> flags,
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}
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// The first two parameters are compile-time constants:
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// * Halving: is the a halving (vhcaddq) or non-halving (vcaddq) instruction
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// * Halving: 0 means halving (vhcaddq), 1 means non-halving (vcaddq)
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// instruction. Note: the flag is inverted to match the corresonding
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// bit in the instruction encoding
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// * Rotation angle: 0 mean 90 deg, 1 means 180 deg
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defm int_arm_mve_vcaddq : MVEMXPredicated<
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[llvm_anyvector_ty],
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@ -233,22 +233,6 @@ private:
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void SelectMVE_VADCSBC(SDNode *N, uint16_t OpcodeWithCarry,
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uint16_t OpcodeWithNoCarry, bool Add, bool Predicated);
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/// Select MVE complex vector addition intrinsic
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/// OpcodesInt are opcodes for non-halving addition of complex integer vectors
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/// OpcodesHInt are opcodes for halving addition of complex integer vectors
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/// OpcodesFP are opcodes for addition of complex floating point vectors
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void SelectMVE_VCADD(SDNode *N, const uint16_t *OpcodesInt,
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const uint16_t *OpcodesHInt, const uint16_t *OpcodesFP,
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bool Predicated);
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/// Select MVE complex vector multiplication intrinsic
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void SelectMVE_VCMUL(SDNode *N, uint16_t OpcodeF16, uint16_t OpcodeF32,
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bool Predicated);
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/// Sekect NVE complex vector multiply-add intrinsic
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void SelectMVE_VCMLA(SDNode *N, uint16_t OpcodeF16, uint16_t OpcodeF32,
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bool Predicated);
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/// SelectMVE_VLD - Select MVE interleaving load intrinsics. NumVecs
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/// should be 2 or 4. The opcode array specifies the instructions
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/// used for 8, 16 and 32-bit lane sizes respectively, and each
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@ -2533,138 +2517,6 @@ void ARMDAGToDAGISel::SelectMVE_VADCSBC(SDNode *N, uint16_t OpcodeWithCarry,
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CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops));
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}
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/// Convert an SDValue to a boolean value. SDVal must be a compile-time constant
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static bool SDValueToConstBool(SDValue SDVal) {
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ConstantSDNode *SDValConstant = dyn_cast<ConstantSDNode>(SDVal);
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assert(SDValConstant && "expected a compile-time constant");
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uint64_t Value = SDValConstant->getZExtValue();
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assert((Value == 0 || Value == 1) && "expected value 0 or 1");
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return Value;
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}
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/// Select an opcode based on a floating point vector type. One opcode
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/// corresponds to 16-bit floating point element type, the other to two 32-bit
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/// element type.
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/// Other types are not allowed
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static uint16_t SelectFPOpcode(EVT VT, uint16_t OpcodeF16, uint16_t OpcodeF32) {
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assert(VT.isFloatingPoint() && VT.isVector() &&
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"expected a floating-point vector");
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switch (VT.getVectorElementType().getSizeInBits()) {
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case 16:
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return OpcodeF16;
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case 32:
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return OpcodeF32;
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default:
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llvm_unreachable("bad vector element size");
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}
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}
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void ARMDAGToDAGISel::SelectMVE_VCADD(SDNode *N, const uint16_t *OpcodesInt,
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const uint16_t *OpcodesHInt,
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const uint16_t *OpcodesFP,
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bool Predicated) {
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EVT VT = N->getValueType(0);
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SDLoc Loc(N);
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bool IsHalved = SDValueToConstBool(N->getOperand(1));
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bool IsAngle270 = SDValueToConstBool(N->getOperand(2));
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bool IsFP = VT.isFloatingPoint();
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if (IsHalved)
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assert(!IsFP && "vhcaddq requires integer vector type");
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uint16_t Opcode;
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if (IsFP) {
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Opcode = SelectFPOpcode(VT, OpcodesFP[0], OpcodesFP[1]);
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} else {
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const uint16_t *Opcodes = IsHalved ? OpcodesHInt : OpcodesInt;
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switch (VT.getVectorElementType().getSizeInBits()) {
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case 8:
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Opcode = Opcodes[0];
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break;
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case 16:
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Opcode = Opcodes[1];
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break;
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case 32:
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Opcode = Opcodes[2];
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break;
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default:
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llvm_unreachable("bad vector element size");
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}
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}
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int FirstInputOp = Predicated ? 4 : 3;
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SmallVector<SDValue, 8> Ops;
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// Vectors
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Ops.push_back(N->getOperand(FirstInputOp));
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Ops.push_back(N->getOperand(FirstInputOp + 1));
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// Rotation
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Ops.push_back(CurDAG->getTargetConstant(IsAngle270, Loc, MVT::i32));
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if (Predicated)
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AddMVEPredicateToOps(Ops, Loc,
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N->getOperand(FirstInputOp + 2), // predicate
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N->getOperand(FirstInputOp - 1)); // inactive
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else
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AddEmptyMVEPredicateToOps(Ops, Loc, VT);
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CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops));
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}
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static uint32_t GetCMulRotation(SDValue V) {
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const ConstantSDNode *RotConstant = dyn_cast<ConstantSDNode>(V);
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assert(RotConstant && "expected a compile-time constant");
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uint64_t RotValue = RotConstant->getZExtValue();
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assert(RotValue < 4 && "expected value in range [0, 3]");
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return RotValue;
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}
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void ARMDAGToDAGISel::SelectMVE_VCMUL(SDNode *N, uint16_t OpcodeF16,
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uint16_t OpcodeF32, bool Predicated) {
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EVT VT = N->getValueType(0);
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SDLoc Loc(N);
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int FirstInputOp = Predicated ? 3 : 2;
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SmallVector<SDValue, 8> Ops;
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// Vectors
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Ops.push_back(N->getOperand(FirstInputOp));
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Ops.push_back(N->getOperand(FirstInputOp + 1));
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// Rotation
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uint32_t RotValue = GetCMulRotation(N->getOperand(1));
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Ops.push_back(CurDAG->getTargetConstant(RotValue, Loc, MVT::i32));
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if (Predicated)
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AddMVEPredicateToOps(Ops, Loc,
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N->getOperand(FirstInputOp + 2), // predicate
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N->getOperand(FirstInputOp - 1)); // inactive
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else
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AddEmptyMVEPredicateToOps(Ops, Loc, VT);
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uint16_t Opcode = SelectFPOpcode(VT, OpcodeF16, OpcodeF32);
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CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops));
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}
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void ARMDAGToDAGISel::SelectMVE_VCMLA(SDNode *N, uint16_t OpcodeF16,
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uint16_t OpcodeF32, bool Predicated) {
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SDLoc Loc(N);
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SmallVector<SDValue, 8> Ops;
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// The 3 vector operands
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for (int i = 2; i < 5; ++i)
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Ops.push_back(N->getOperand(i));
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// Rotation
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uint32_t RotValue = GetCMulRotation(N->getOperand(1));
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Ops.push_back(CurDAG->getTargetConstant(RotValue, Loc, MVT::i32));
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if (Predicated)
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AddMVEPredicateToOps(Ops, Loc, N->getOperand(5));
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else
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AddEmptyMVEPredicateToOps(Ops, Loc);
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EVT VT = N->getValueType(0);
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uint16_t Opcode = SelectFPOpcode(VT, OpcodeF16, OpcodeF32);
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CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops));
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}
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void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs,
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const uint16_t *const *Opcodes) {
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EVT VT = N->getValueType(0);
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@ -4510,35 +4362,6 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
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IntNo == Intrinsic::arm_mve_vadc_predicated);
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return;
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case Intrinsic::arm_mve_vcaddq:
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case Intrinsic::arm_mve_vcaddq_predicated: {
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static const uint16_t OpcodesInt[] = {
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ARM::MVE_VCADDi8, ARM::MVE_VCADDi16, ARM::MVE_VCADDi32,
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};
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static const uint16_t OpcodesHInt[] = {
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ARM::MVE_VHCADDs8, ARM::MVE_VHCADDs16, ARM::MVE_VHCADDs32,
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};
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static const uint16_t OpcodesFP[] = {
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ARM::MVE_VCADDf16, ARM::MVE_VCADDf32,
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};
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SelectMVE_VCADD(N, OpcodesInt, OpcodesHInt,
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OpcodesFP, IntNo == Intrinsic::arm_mve_vcaddq_predicated);
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return;
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}
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case Intrinsic::arm_mve_vcmulq:
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case Intrinsic::arm_mve_vcmulq_predicated:
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SelectMVE_VCMUL(N, ARM::MVE_VCMULf16, ARM::MVE_VCMULf32,
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IntNo == Intrinsic::arm_mve_vcmulq_predicated);
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return;
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case Intrinsic::arm_mve_vcmlaq:
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case Intrinsic::arm_mve_vcmlaq_predicated:
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SelectMVE_VCMLA(N, ARM::MVE_VCMLAf16, ARM::MVE_VCMLAf32,
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IntNo == Intrinsic::arm_mve_vcmlaq_predicated);
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return;
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}
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break;
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}
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@ -2960,10 +2960,10 @@ multiclass MVE_VMUL_fp_m<MVEVectorVTInfo VTI>
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defm MVE_VMULf32 : MVE_VMUL_fp_m<MVE_v4f32>;
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defm MVE_VMULf16 : MVE_VMUL_fp_m<MVE_v8f16>;
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class MVE_VCMLA<string suffix, bit size, list<dag> pattern=[]>
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class MVE_VCMLA<string suffix, bit size>
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: MVEFloatArithNeon<"vcmla", suffix, size, (outs MQPR:$Qd),
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(ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
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"$Qd, $Qn, $Qm, $rot", vpred_n, "$Qd = $Qd_src", pattern> {
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"$Qd, $Qn, $Qm, $rot", vpred_n, "$Qd = $Qd_src", []> {
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bits<4> Qd;
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bits<4> Qn;
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bits<2> rot;
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@ -2980,8 +2980,32 @@ class MVE_VCMLA<string suffix, bit size, list<dag> pattern=[]>
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let Inst{4} = 0b0;
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}
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def MVE_VCMLAf16 : MVE_VCMLA<"f16", 0b0>;
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def MVE_VCMLAf32 : MVE_VCMLA<"f32", 0b1>;
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multiclass MVE_VCMLA_m<MVEVectorVTInfo VTI, bit size> {
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def "" : MVE_VCMLA<VTI.Suffix, size>;
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let Predicates = [HasMVEFloat] in {
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def : Pat<(VTI.Vec (int_arm_mve_vcmlaq
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imm:$rot, (VTI.Vec MQPR:$Qd_src),
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(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
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(VTI.Vec (!cast<Instruction>(NAME)
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(VTI.Vec MQPR:$Qd_src),
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(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
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imm:$rot))>;
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def : Pat<(VTI.Vec (int_arm_mve_vcmlaq_predicated
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imm:$rot, (VTI.Vec MQPR:$Qd_src),
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(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
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(VTI.Pred VCCR:$mask))),
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(VTI.Vec (!cast<Instruction>(NAME)
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(VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qn),
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(VTI.Vec MQPR:$Qm), imm:$rot,
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ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
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}
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}
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defm MVE_VCMLAf16 : MVE_VCMLA_m<MVE_v8f16, 0b0>;
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defm MVE_VCMLAf32 : MVE_VCMLA_m<MVE_v4f32, 0b1>;
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class MVE_VADDSUBFMA_fp<string iname, string suffix, bit size, bit bit_4,
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bit bit_8, bit bit_21, dag iops=(ins),
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@ -3056,10 +3080,10 @@ defm MVE_VADDf16 : MVE_VADD_fp_m<MVE_v8f16>;
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defm MVE_VSUBf32 : MVE_VSUB_fp_m<MVE_v4f32>;
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defm MVE_VSUBf16 : MVE_VSUB_fp_m<MVE_v8f16>;
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class MVE_VCADD<string suffix, bit size, string cstr="", list<dag> pattern=[]>
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class MVE_VCADD<string suffix, bit size, string cstr="">
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: MVEFloatArithNeon<"vcadd", suffix, size, (outs MQPR:$Qd),
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(ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
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"$Qd, $Qn, $Qm, $rot", vpred_r, cstr, pattern> {
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"$Qd, $Qn, $Qm, $rot", vpred_r, cstr, []> {
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bits<4> Qd;
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bits<4> Qn;
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bit rot;
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@ -3077,8 +3101,31 @@ class MVE_VCADD<string suffix, bit size, string cstr="", list<dag> pattern=[]>
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let Inst{4} = 0b0;
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}
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def MVE_VCADDf16 : MVE_VCADD<"f16", 0b0>;
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def MVE_VCADDf32 : MVE_VCADD<"f32", 0b1, "@earlyclobber $Qd">;
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multiclass MVE_VCADD_m<MVEVectorVTInfo VTI, bit size, string cstr=""> {
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def "" : MVE_VCADD<VTI.Suffix, size, cstr>;
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let Predicates = [HasMVEFloat] in {
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def : Pat<(VTI.Vec (int_arm_mve_vcaddq (i32 1),
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imm:$rot, (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
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(VTI.Vec (!cast<Instruction>(NAME)
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(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
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imm:$rot))>;
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def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated (i32 1),
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imm:$rot, (VTI.Vec MQPR:$inactive),
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(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
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(VTI.Pred VCCR:$mask))),
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(VTI.Vec (!cast<Instruction>(NAME)
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(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
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imm:$rot,
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ARMVCCThen, (VTI.Pred VCCR:$mask),
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(VTI.Vec MQPR:$inactive)))>;
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}
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}
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defm MVE_VCADDf16 : MVE_VCADD_m<MVE_v8f16, 0b0>;
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defm MVE_VCADDf32 : MVE_VCADD_m<MVE_v4f32, 0b1, "@earlyclobber $Qd">;
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class MVE_VABD_fp<string suffix, bit size>
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: MVE_float<"vabd", suffix, (outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
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@ -3690,10 +3737,10 @@ defm MVE_VQDMLSDHX : MVE_VQxDMLxDH_multi<"vqdmlsdhx", 0b1, 0b0, 0b1>;
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defm MVE_VQRDMLSDH : MVE_VQxDMLxDH_multi<"vqrdmlsdh", 0b0, 0b1, 0b1>;
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defm MVE_VQRDMLSDHX : MVE_VQxDMLxDH_multi<"vqrdmlsdhx", 0b1, 0b1, 0b1>;
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class MVE_VCMUL<string iname, string suffix, bit size, string cstr="", list<dag> pattern=[]>
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class MVE_VCMUL<string iname, string suffix, bit size, string cstr="">
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: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
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(ins MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
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"$Qd, $Qn, $Qm, $rot", vpred_r, cstr, pattern> {
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"$Qd, $Qn, $Qm, $rot", vpred_r, cstr, []> {
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bits<4> Qn;
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bits<2> rot;
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@ -3709,8 +3756,33 @@ class MVE_VCMUL<string iname, string suffix, bit size, string cstr="", list<dag>
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let Predicates = [HasMVEFloat];
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}
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def MVE_VCMULf16 : MVE_VCMUL<"vcmul", "f16", 0b0>;
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def MVE_VCMULf32 : MVE_VCMUL<"vcmul", "f32", 0b1, "@earlyclobber $Qd">;
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multiclass MVE_VCMUL_m<string iname, MVEVectorVTInfo VTI,
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bit size, string cstr=""> {
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def "" : MVE_VCMUL<iname, VTI.Suffix, size, cstr>;
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let Predicates = [HasMVEFloat] in {
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def : Pat<(VTI.Vec (int_arm_mve_vcmulq
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imm:$rot, (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
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(VTI.Vec (!cast<Instruction>(NAME)
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(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
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imm:$rot))>;
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def : Pat<(VTI.Vec (int_arm_mve_vcmulq_predicated
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imm:$rot, (VTI.Vec MQPR:$inactive),
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(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
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(VTI.Pred VCCR:$mask))),
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(VTI.Vec (!cast<Instruction>(NAME)
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(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
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imm:$rot,
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ARMVCCThen, (VTI.Pred VCCR:$mask),
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(VTI.Vec MQPR:$inactive)))>;
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}
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}
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defm MVE_VCMULf16 : MVE_VCMUL_m<"vcmul", MVE_v8f16, 0b0>;
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defm MVE_VCMULf32 : MVE_VCMUL_m<"vcmul", MVE_v4f32, 0b1, "@earlyclobber $Qd">;
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class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
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bit T, string cstr, list<dag> pattern=[]>
|
||||
@ -3938,10 +4010,10 @@ defm MVE_VCVTf32f16bh : MVE_VCVT_h2f_m<"vcvtb", 0b0>;
|
||||
defm MVE_VCVTf32f16th : MVE_VCVT_h2f_m<"vcvtt", 0b1>;
|
||||
|
||||
class MVE_VxCADD<string iname, string suffix, bits<2> size, bit halve,
|
||||
string cstr="", list<dag> pattern=[]>
|
||||
string cstr="">
|
||||
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
|
||||
(ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
|
||||
"$Qd, $Qn, $Qm, $rot", vpred_r, cstr, pattern> {
|
||||
"$Qd, $Qn, $Qm, $rot", vpred_r, cstr, []> {
|
||||
bits<4> Qn;
|
||||
bit rot;
|
||||
|
||||
@ -3955,13 +4027,37 @@ class MVE_VxCADD<string iname, string suffix, bits<2> size, bit halve,
|
||||
let Inst{0} = 0b0;
|
||||
}
|
||||
|
||||
def MVE_VCADDi8 : MVE_VxCADD<"vcadd", "i8", 0b00, 0b1>;
|
||||
def MVE_VCADDi16 : MVE_VxCADD<"vcadd", "i16", 0b01, 0b1>;
|
||||
def MVE_VCADDi32 : MVE_VxCADD<"vcadd", "i32", 0b10, 0b1, "@earlyclobber $Qd">;
|
||||
multiclass MVE_VxCADD_m<string iname, MVEVectorVTInfo VTI,
|
||||
bit halve, string cstr=""> {
|
||||
def "" : MVE_VxCADD<iname, VTI.Suffix, VTI.Size, halve, cstr>;
|
||||
|
||||
def MVE_VHCADDs8 : MVE_VxCADD<"vhcadd", "s8", 0b00, 0b0>;
|
||||
def MVE_VHCADDs16 : MVE_VxCADD<"vhcadd", "s16", 0b01, 0b0>;
|
||||
def MVE_VHCADDs32 : MVE_VxCADD<"vhcadd", "s32", 0b10, 0b0, "@earlyclobber $Qd">;
|
||||
let Predicates = [HasMVEInt] in {
|
||||
def : Pat<(VTI.Vec (int_arm_mve_vcaddq halve,
|
||||
imm:$rot, (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
|
||||
(VTI.Vec (!cast<Instruction>(NAME)
|
||||
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
|
||||
imm:$rot))>;
|
||||
|
||||
def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated halve,
|
||||
imm:$rot, (VTI.Vec MQPR:$inactive),
|
||||
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
|
||||
(VTI.Pred VCCR:$mask))),
|
||||
(VTI.Vec (!cast<Instruction>(NAME)
|
||||
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
|
||||
imm:$rot,
|
||||
ARMVCCThen, (VTI.Pred VCCR:$mask),
|
||||
(VTI.Vec MQPR:$inactive)))>;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
defm MVE_VCADDi8 : MVE_VxCADD_m<"vcadd", MVE_v16i8, 0b1>;
|
||||
defm MVE_VCADDi16 : MVE_VxCADD_m<"vcadd", MVE_v8i16, 0b1>;
|
||||
defm MVE_VCADDi32 : MVE_VxCADD_m<"vcadd", MVE_v4i32, 0b1, "@earlyclobber $Qd">;
|
||||
|
||||
defm MVE_VHCADDs8 : MVE_VxCADD_m<"vhcadd", MVE_v16s8, 0b0>;
|
||||
defm MVE_VHCADDs16 : MVE_VxCADD_m<"vhcadd", MVE_v8s16, 0b0>;
|
||||
defm MVE_VHCADDs32 : MVE_VxCADD_m<"vhcadd", MVE_v4s32, 0b0, "@earlyclobber $Qd">;
|
||||
|
||||
class MVE_VADCSBC<string iname, bit I, bit subtract,
|
||||
dag carryin, list<dag> pattern=[]>
|
||||
|
||||
@ -23,7 +23,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> %a, <16 x i8> %
|
||||
; CHECK-NEXT: vcadd.i8 q0, q0, q1, #90
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %a, <16 x i8> %b)
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %a, <16 x i8> %b)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
|
||||
@ -33,7 +33,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> %a, <8 x i16>
|
||||
; CHECK-NEXT: vcadd.i16 q0, q0, q1, #90
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %a, <8 x i16> %b)
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %a, <8 x i16> %b)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
|
||||
@ -44,7 +44,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> %a, <4 x i32>
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %a, <4 x i32> %b)
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %a, <4 x i32> %b)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
@ -54,7 +54,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> %a, <16 x i8> %
|
||||
; CHECK-NEXT: vcadd.i8 q0, q0, q1, #90
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %a, <16 x i8> %b)
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %a, <16 x i8> %b)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
|
||||
@ -64,7 +64,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> %a, <8 x i16>
|
||||
; CHECK-NEXT: vcadd.i16 q0, q0, q1, #90
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %a, <8 x i16> %b)
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %a, <8 x i16> %b)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
|
||||
@ -75,7 +75,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> %a, <4 x i32>
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %a, <4 x i32> %b)
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %a, <4 x i32> %b)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
@ -85,7 +85,7 @@ define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> %a, <8 x hal
|
||||
; CHECK-NEXT: vcadd.f16 q0, q0, q1, #90
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 0, i32 0, <8 x half> %a, <8 x half> %b)
|
||||
%0 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %a, <8 x half> %b)
|
||||
ret <8 x half> %0
|
||||
}
|
||||
|
||||
@ -96,7 +96,7 @@ define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> %a, <4 x f
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 0, i32 0, <4 x float> %a, <4 x float> %b)
|
||||
%0 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %a, <4 x float> %b)
|
||||
ret <4 x float> %0
|
||||
}
|
||||
|
||||
@ -106,7 +106,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> %a, <16 x i8>
|
||||
; CHECK-NEXT: vcadd.i8 q0, q0, q1, #270
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %a, <16 x i8> %b)
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %a, <16 x i8> %b)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
|
||||
@ -116,7 +116,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> %a, <8 x i16>
|
||||
; CHECK-NEXT: vcadd.i16 q0, q0, q1, #270
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %a, <8 x i16> %b)
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %a, <8 x i16> %b)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
|
||||
@ -127,7 +127,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> %a, <4 x i32>
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %a, <4 x i32> %b)
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %a, <4 x i32> %b)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
@ -137,7 +137,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> %a, <16 x i8>
|
||||
; CHECK-NEXT: vcadd.i8 q0, q0, q1, #270
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %a, <16 x i8> %b)
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %a, <16 x i8> %b)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
|
||||
@ -147,7 +147,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> %a, <8 x i16>
|
||||
; CHECK-NEXT: vcadd.i16 q0, q0, q1, #270
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %a, <8 x i16> %b)
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %a, <8 x i16> %b)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
|
||||
@ -158,7 +158,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> %a, <4 x i32>
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %a, <4 x i32> %b)
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %a, <4 x i32> %b)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
@ -168,7 +168,7 @@ define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> %a, <8 x ha
|
||||
; CHECK-NEXT: vcadd.f16 q0, q0, q1, #270
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 0, i32 1, <8 x half> %a, <8 x half> %b)
|
||||
%0 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %a, <8 x half> %b)
|
||||
ret <8 x half> %0
|
||||
}
|
||||
|
||||
@ -179,7 +179,7 @@ define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> %a, <4 x
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 0, i32 1, <4 x float> %a, <4 x float> %b)
|
||||
%0 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %a, <4 x float> %b)
|
||||
ret <4 x float> %0
|
||||
}
|
||||
|
||||
@ -193,7 +193,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> %inactive, <1
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -207,7 +207,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_m_u16(<8 x i16> %inactive, <
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -221,7 +221,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_m_u32(<4 x i32> %inactive, <
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -235,7 +235,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_s8(<16 x i8> %inactive, <1
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -249,7 +249,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_m_s16(<8 x i16> %inactive, <
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -263,7 +263,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_m_s32(<4 x i32> %inactive, <
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -277,7 +277,7 @@ define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_m_f16(<8 x half> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 0, i32 0, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
|
||||
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 0, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
|
||||
ret <8 x half> %2
|
||||
}
|
||||
|
||||
@ -291,7 +291,7 @@ define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_m_f32(<4 x float> %inactiv
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 0, i32 0, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
|
||||
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 0, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
|
||||
ret <4 x float> %2
|
||||
}
|
||||
|
||||
@ -305,7 +305,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_m_u8(<16 x i8> %inactive, <
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -319,7 +319,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_m_u16(<8 x i16> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -333,7 +333,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_m_u32(<4 x i32> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -347,7 +347,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_m_s8(<16 x i8> %inactive, <
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -361,7 +361,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_m_s16(<8 x i16> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -375,7 +375,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_m_s32(<4 x i32> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -389,7 +389,7 @@ define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_m_f16(<8 x half> %inactive
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 0, i32 1, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
|
||||
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 1, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
|
||||
ret <8 x half> %2
|
||||
}
|
||||
|
||||
@ -403,7 +403,7 @@ define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_m_f32(<4 x float> %inacti
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 0, i32 1, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
|
||||
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 1, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
|
||||
ret <4 x float> %2
|
||||
}
|
||||
|
||||
@ -417,7 +417,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_x_u8(<16 x i8> %a, <16 x i8>
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -431,7 +431,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_x_u16(<8 x i16> %a, <8 x i16
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -446,7 +446,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_x_u32(<4 x i32> %a, <4 x i32
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -460,7 +460,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_x_s8(<16 x i8> %a, <16 x i8>
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -474,7 +474,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_x_s16(<8 x i16> %a, <8 x i16
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -489,7 +489,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_x_s32(<4 x i32> %a, <4 x i32
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -503,7 +503,7 @@ define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_x_f16(<8 x half> %a, <8 x h
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 0, i32 0, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
|
||||
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 0, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
|
||||
ret <8 x half> %2
|
||||
}
|
||||
|
||||
@ -518,7 +518,7 @@ define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_x_f32(<4 x float> %a, <4 x
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 0, i32 0, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
|
||||
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 0, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
|
||||
ret <4 x float> %2
|
||||
}
|
||||
|
||||
@ -532,7 +532,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_x_u8(<16 x i8> %a, <16 x i8
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -546,7 +546,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_x_u16(<8 x i16> %a, <8 x i1
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -561,7 +561,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_x_u32(<4 x i32> %a, <4 x i3
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -575,7 +575,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_x_s8(<16 x i8> %a, <16 x i8
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -589,7 +589,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_x_s16(<8 x i16> %a, <8 x i1
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -604,7 +604,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_x_s32(<4 x i32> %a, <4 x i3
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -618,7 +618,7 @@ define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_x_f16(<8 x half> %a, <8 x
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 0, i32 1, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
|
||||
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 1, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
|
||||
ret <8 x half> %2
|
||||
}
|
||||
|
||||
@ -633,7 +633,7 @@ define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_x_f32(<4 x float> %a, <4
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 0, i32 1, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
|
||||
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 1, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
|
||||
ret <4 x float> %2
|
||||
}
|
||||
|
||||
@ -643,7 +643,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> %a, <16 x i8>
|
||||
; CHECK-NEXT: vhcadd.s8 q0, q0, q1, #90
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %a, <16 x i8> %b)
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %a, <16 x i8> %b)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
|
||||
@ -653,7 +653,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> %a, <8 x i16>
|
||||
; CHECK-NEXT: vhcadd.s16 q0, q0, q1, #90
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %a, <8 x i16> %b)
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %a, <8 x i16> %b)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
|
||||
@ -664,7 +664,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> %a, <4 x i32>
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %a, <4 x i32> %b)
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %a, <4 x i32> %b)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
@ -674,7 +674,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> %a, <16 x i8>
|
||||
; CHECK-NEXT: vhcadd.s8 q0, q0, q1, #270
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %a, <16 x i8> %b)
|
||||
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %a, <16 x i8> %b)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
|
||||
@ -684,7 +684,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> %a, <8 x i16
|
||||
; CHECK-NEXT: vhcadd.s16 q0, q0, q1, #270
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %a, <8 x i16> %b)
|
||||
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %a, <8 x i16> %b)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
|
||||
@ -695,7 +695,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> %a, <4 x i32
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %a, <4 x i32> %b)
|
||||
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %a, <4 x i32> %b)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
@ -709,7 +709,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> %a, <16 x i8
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -723,7 +723,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> %a, <8 x i1
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -738,7 +738,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> %a, <4 x i3
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -752,7 +752,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> %a, <16 x i
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -766,7 +766,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> %a, <8 x i
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -781,7 +781,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> %a, <4 x i
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -795,7 +795,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> %inactive, <
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -809,7 +809,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_m_s16(<8 x i16> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -823,7 +823,7 @@ define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_m_s32(<4 x i32> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
@ -837,7 +837,7 @@ define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_m_s8(<16 x i8> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
|
||||
ret <16 x i8> %2
|
||||
}
|
||||
|
||||
@ -851,7 +851,7 @@ define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_m_s16(<8 x i16> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
|
||||
ret <8 x i16> %2
|
||||
}
|
||||
|
||||
@ -865,6 +865,6 @@ define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_m_s32(<4 x i32> %inactive,
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user