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AMDGPU: Don't reserve SCRATCH_PTR input register

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This hasn't been doing anything since using relocations was added.

llvm-svn: 254304
This commit is contained in:
Matt Arsenault 2015-11-30 15:46:47 +00:00
parent b3f88e2a89
commit 73a891e5c6
2 changed files with 5 additions and 13 deletions
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16
lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -633,21 +633,13 @@ SDValue SITargetLowering::LowerFormalArguments(
unsigned InputPtrRegHi =
TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1);
unsigned ScratchPtrReg =
TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
unsigned ScratchPtrRegLo =
TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0);
unsigned ScratchPtrRegHi =
TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1);
CCInfo.AllocateReg(InputPtrRegLo);
CCInfo.AllocateReg(InputPtrRegHi);
CCInfo.AllocateReg(ScratchPtrRegLo);
CCInfo.AllocateReg(ScratchPtrRegHi);
MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
if (Subtarget->isAmdHsaOS() && MFI->hasDispatchPtr()) {
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
if (MFI->hasDispatchPtr()) {
unsigned DispatchPtrReg =
TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR);
unsigned DispatchPtrRegLo =

2
test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
View File

@ -3,7 +3,7 @@
; register operands in the correct order when modifying the opcode of an
; instruction to V_ADD_I32_e32.
; CHECK: %19 = V_ADD_I32_e32 %13, %12, implicit-def %vcc, implicit %exec
; CHECK: %{{[0-9]+}} = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec
define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
entry: