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[RISCV] Add support for fixed vector vselect
This patch adds support for fixed-length vector vselect. It does so by lowering them to a custom unmasked VSELECT_VL node with a vector length operand. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D96768
This commit is contained in:
Fraser Cormack
parent
3342619547
commit
73b0930caf
@ -558,6 +558,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SMAX, VT, Custom);
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setOperationAction(ISD::UMIN, VT, Custom);
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setOperationAction(ISD::UMAX, VT, Custom);
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setOperationAction(ISD::VSELECT, VT, Custom);
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}
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for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) {
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@ -587,6 +589,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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for (auto CC : VFPCCToExpand)
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setCondCodeAction(CC, VT, Expand);
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setOperationAction(ISD::VSELECT, VT, Custom);
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}
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}
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}
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@ -1258,6 +1262,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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return lowerToScalableOp(Op, DAG, RISCVISD::UMIN_VL);
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case ISD::UMAX:
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return lowerToScalableOp(Op, DAG, RISCVISD::UMAX_VL);
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case ISD::VSELECT:
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return lowerFixedLengthVectorSelectToRVV(Op, DAG);
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}
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}
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@ -2247,6 +2253,31 @@ SDValue RISCVTargetLowering::lowerFixedLengthVectorLogicOpToRVV(
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return lowerToScalableOp(Op, DAG, VecOpc, /*HasMask*/ true);
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}
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SDValue RISCVTargetLowering::lowerFixedLengthVectorSelectToRVV(
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SDValue Op, SelectionDAG &DAG) const {
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MVT VT = Op.getSimpleValueType();
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MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
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MVT I1ContainerVT =
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MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount());
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SDValue CC =
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convertToScalableVector(I1ContainerVT, Op.getOperand(0), DAG, Subtarget);
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SDValue Op1 =
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convertToScalableVector(ContainerVT, Op.getOperand(1), DAG, Subtarget);
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SDValue Op2 =
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convertToScalableVector(ContainerVT, Op.getOperand(2), DAG, Subtarget);
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SDLoc DL(Op);
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SDValue Mask, VL;
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std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
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SDValue Select =
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DAG.getNode(RISCVISD::VSELECT_VL, DL, ContainerVT, CC, Op1, Op2, VL);
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return convertFromScalableVector(VT, Select, DAG, Subtarget);
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}
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SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op, SelectionDAG &DAG,
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unsigned NewOpc,
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bool HasMask) const {
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@ -4906,6 +4937,7 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(UMIN_VL)
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NODE_NAME_CASE(UMAX_VL)
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NODE_NAME_CASE(SETCC_VL)
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NODE_NAME_CASE(VSELECT_VL)
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NODE_NAME_CASE(VMAND_VL)
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NODE_NAME_CASE(VMOR_VL)
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NODE_NAME_CASE(VMXOR_VL)
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@ -175,6 +175,9 @@ enum NodeType : unsigned {
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// operand is VL.
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SETCC_VL,
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// Vector select with an additional VL operand. This operation is unmasked.
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VSELECT_VL,
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// Mask binary operators.
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VMAND_VL,
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VMOR_VL,
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@ -410,6 +413,8 @@ private:
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SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
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unsigned MaskOpc,
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unsigned VecOpc) const;
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SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
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SelectionDAG &DAG) const;
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SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
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bool HasMask = true) const;
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@ -111,6 +111,15 @@ def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL",
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SDTCisSameNumEltsAs<0, 3>,
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SDTCisVT<4, XLenVT>]>>;
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def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL",
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SDTypeProfile<1, 4, [SDTCisVec<0>,
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SDTCisVec<1>,
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SDTCisSameNumEltsAs<0, 1>,
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SDTCVecEltisVT<1, i1>,
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SDTCisSameAs<0, 2>,
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SDTCisSameAs<2, 3>,
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SDTCisVT<4, XLenVT>]>>;
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def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCVecEltisVT<0, i1>,
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@ -441,6 +450,31 @@ defm "" : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">;
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defm "" : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">;
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defm "" : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">;
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// 12.16. Vector Integer Merge Instructions
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foreach vti = AllIntegerVectors in {
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def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask VMV0:$vm),
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vti.RegClass:$rs1,
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vti.RegClass:$rs2,
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX)
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vti.RegClass:$rs2, vti.RegClass:$rs1, VMV0:$vm,
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GPR:$vl, vti.SEW)>;
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def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask VMV0:$vm),
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(SplatPat XLenVT:$rs1),
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vti.RegClass:$rs2,
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX)
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vti.RegClass:$rs2, GPR:$rs1, VMV0:$vm, GPR:$vl, vti.SEW)>;
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def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask VMV0:$vm),
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(SplatPat_simm5 simm5:$rs1),
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vti.RegClass:$rs2,
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX)
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vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, GPR:$vl, vti.SEW)>;
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}
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// 12.17. Vector Integer Move Instructions
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foreach vti = AllIntegerVectors in {
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def : Pat<(vti.Vector (riscv_vmv_v_x_vl GPR:$rs2, (XLenVT (VLOp GPR:$vl)))),
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@ -609,8 +643,35 @@ foreach vti = AllFloatVectors in {
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vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.SEW)>;
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}
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// 14.16. Vector Floating-Point Move Instruction
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foreach fvti = AllFloatVectors in {
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// Floating-point vselects:
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// 12.16. Vector Integer Merge Instructions
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// 14.13. Vector Floating-Point Merge Instruction
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def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask VMV0:$vm),
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fvti.RegClass:$rs1,
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fvti.RegClass:$rs2,
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX)
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fvti.RegClass:$rs2, fvti.RegClass:$rs1, VMV0:$vm,
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GPR:$vl, fvti.SEW)>;
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def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask VMV0:$vm),
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(SplatFPOp fvti.ScalarRegClass:$rs1),
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fvti.RegClass:$rs2,
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX)
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fvti.RegClass:$rs2,
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(fvti.Scalar fvti.ScalarRegClass:$rs1),
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VMV0:$vm, GPR:$vl, fvti.SEW)>;
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def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask VMV0:$vm),
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(SplatFPOp (fvti.Scalar fpimm0)),
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fvti.RegClass:$rs2,
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
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fvti.RegClass:$rs2, 0, VMV0:$vm, GPR:$vl, fvti.SEW)>;
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// 14.16. Vector Floating-Point Move Instruction
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// If we're splatting fpimm0, use vmv.v.x vd, x0.
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def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
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(fvti.Scalar (fpimm0)), (XLenVT (VLOp GPR:$vl)))),
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255
test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
Normal file
255
test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
Normal file
@ -0,0 +1,255 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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define void @vselect_vv_v8i32(<8 x i32>* %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
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; CHECK-LABEL: vselect_vv_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a4, zero, 8
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; CHECK-NEXT: vsetvli a5, a4, e32,m2,ta,mu
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; CHECK-NEXT: vle32.v v26, (a0)
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; CHECK-NEXT: vle32.v v28, (a1)
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; CHECK-NEXT: vsetvli a0, a4, e8,m1,ta,mu
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; CHECK-NEXT: vle1.v v0, (a2)
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; CHECK-NEXT: vsetvli a0, a4, e32,m2,ta,mu
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; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0
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; CHECK-NEXT: vse32.v v26, (a3)
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; CHECK-NEXT: ret
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%va = load <8 x i32>, <8 x i32>* %a
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%vb = load <8 x i32>, <8 x i32>* %b
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%vcc = load <8 x i1>, <8 x i1>* %cc
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%vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb
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store <8 x i32> %vsel, <8 x i32>* %z
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ret void
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}
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define void @vselect_vx_v8i32(i32 %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
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; CHECK-LABEL: vselect_vx_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a4, zero, 8
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; CHECK-NEXT: vsetvli a5, a4, e32,m2,ta,mu
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; CHECK-NEXT: vle32.v v26, (a1)
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; CHECK-NEXT: vsetvli a1, a4, e8,m1,ta,mu
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; CHECK-NEXT: vle1.v v0, (a2)
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; CHECK-NEXT: vsetvli a1, a4, e32,m2,ta,mu
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; CHECK-NEXT: vmerge.vxm v26, v26, a0, v0
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; CHECK-NEXT: vse32.v v26, (a3)
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; CHECK-NEXT: ret
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%vb = load <8 x i32>, <8 x i32>* %b
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%ahead = insertelement <8 x i32> undef, i32 %a, i32 0
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%va = shufflevector <8 x i32> %ahead, <8 x i32> undef, <8 x i32> zeroinitializer
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%vcc = load <8 x i1>, <8 x i1>* %cc
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%vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb
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store <8 x i32> %vsel, <8 x i32>* %z
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ret void
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}
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define void @vselect_vi_v8i32(<8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
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; CHECK-LABEL: vselect_vi_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a3, zero, 8
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; CHECK-NEXT: vsetvli a4, a3, e32,m2,ta,mu
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; CHECK-NEXT: vle32.v v26, (a0)
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; CHECK-NEXT: vsetvli a0, a3, e8,m1,ta,mu
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; CHECK-NEXT: vle1.v v0, (a1)
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; CHECK-NEXT: vsetvli a0, a3, e32,m2,ta,mu
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; CHECK-NEXT: vmerge.vim v26, v26, -1, v0
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; CHECK-NEXT: vse32.v v26, (a2)
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; CHECK-NEXT: ret
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%vb = load <8 x i32>, <8 x i32>* %b
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%a = insertelement <8 x i32> undef, i32 -1, i32 0
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%va = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
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%vcc = load <8 x i1>, <8 x i1>* %cc
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%vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb
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store <8 x i32> %vsel, <8 x i32>* %z
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ret void
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}
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define void @vselect_vv_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x i1>* %cc, <8 x float>* %z) {
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; CHECK-LABEL: vselect_vv_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a4, zero, 8
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; CHECK-NEXT: vsetvli a5, a4, e32,m2,ta,mu
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; CHECK-NEXT: vle32.v v26, (a0)
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; CHECK-NEXT: vle32.v v28, (a1)
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; CHECK-NEXT: vsetvli a0, a4, e8,m1,ta,mu
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; CHECK-NEXT: vle1.v v0, (a2)
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; CHECK-NEXT: vsetvli a0, a4, e32,m2,ta,mu
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; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0
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; CHECK-NEXT: vse32.v v26, (a3)
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; CHECK-NEXT: ret
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%va = load <8 x float>, <8 x float>* %a
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%vb = load <8 x float>, <8 x float>* %b
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%vcc = load <8 x i1>, <8 x i1>* %cc
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%vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb
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store <8 x float> %vsel, <8 x float>* %z
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ret void
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}
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define void @vselect_vx_v8f32(float %a, <8 x float>* %b, <8 x i1>* %cc, <8 x float>* %z) {
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; CHECK-LABEL: vselect_vx_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a3, zero, 8
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; CHECK-NEXT: vsetvli a4, a3, e32,m2,ta,mu
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; CHECK-NEXT: vle32.v v26, (a0)
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; CHECK-NEXT: vsetvli a0, a3, e8,m1,ta,mu
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; CHECK-NEXT: vle1.v v0, (a1)
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; CHECK-NEXT: vsetvli a0, a3, e32,m2,ta,mu
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; CHECK-NEXT: vfmerge.vfm v26, v26, fa0, v0
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; CHECK-NEXT: vse32.v v26, (a2)
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; CHECK-NEXT: ret
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%vb = load <8 x float>, <8 x float>* %b
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%ahead = insertelement <8 x float> undef, float %a, i32 0
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%va = shufflevector <8 x float> %ahead, <8 x float> undef, <8 x i32> zeroinitializer
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%vcc = load <8 x i1>, <8 x i1>* %cc
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%vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb
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store <8 x float> %vsel, <8 x float>* %z
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ret void
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}
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define void @vselect_vfpzero_v8f32(<8 x float>* %b, <8 x i1>* %cc, <8 x float>* %z) {
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; CHECK-LABEL: vselect_vfpzero_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a3, zero, 8
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; CHECK-NEXT: vsetvli a4, a3, e32,m2,ta,mu
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; CHECK-NEXT: vle32.v v26, (a0)
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; CHECK-NEXT: vsetvli a0, a3, e8,m1,ta,mu
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; CHECK-NEXT: vle1.v v0, (a1)
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; CHECK-NEXT: vsetvli a0, a3, e32,m2,ta,mu
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; CHECK-NEXT: vmerge.vim v26, v26, 0, v0
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; CHECK-NEXT: vse32.v v26, (a2)
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; CHECK-NEXT: ret
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%vb = load <8 x float>, <8 x float>* %b
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%a = insertelement <8 x float> undef, float 0.0, i32 0
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%va = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer
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%vcc = load <8 x i1>, <8 x i1>* %cc
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%vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb
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store <8 x float> %vsel, <8 x float>* %z
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ret void
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}
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define void @vselect_vv_v16i16(<16 x i16>* %a, <16 x i16>* %b, <16 x i1>* %cc, <16 x i16>* %z) {
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; CHECK-LABEL: vselect_vv_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a4, zero, 16
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; CHECK-NEXT: vsetvli a5, a4, e16,m2,ta,mu
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; CHECK-NEXT: vle16.v v26, (a0)
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; CHECK-NEXT: vle16.v v28, (a1)
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; CHECK-NEXT: vsetvli a0, a4, e8,m1,ta,mu
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; CHECK-NEXT: vle1.v v0, (a2)
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; CHECK-NEXT: vsetvli a0, a4, e16,m2,ta,mu
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; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0
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; CHECK-NEXT: vse16.v v26, (a3)
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; CHECK-NEXT: ret
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%va = load <16 x i16>, <16 x i16>* %a
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%vb = load <16 x i16>, <16 x i16>* %b
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%vcc = load <16 x i1>, <16 x i1>* %cc
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%vsel = select <16 x i1> %vcc, <16 x i16> %va, <16 x i16> %vb
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store <16 x i16> %vsel, <16 x i16>* %z
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ret void
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}
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define void @vselect_vx_v16i16(i16 signext %a, <16 x i16>* %b, <16 x i1>* %cc, <16 x i16>* %z) {
|
||||
; CHECK-LABEL: vselect_vx_v16i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a4, zero, 16
|
||||
; CHECK-NEXT: vsetvli a5, a4, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vle16.v v26, (a1)
|
||||
; CHECK-NEXT: vsetvli a1, a4, e8,m1,ta,mu
|
||||
; CHECK-NEXT: vle1.v v0, (a2)
|
||||
; CHECK-NEXT: vsetvli a1, a4, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vmerge.vxm v26, v26, a0, v0
|
||||
; CHECK-NEXT: vse16.v v26, (a3)
|
||||
; CHECK-NEXT: ret
|
||||
%vb = load <16 x i16>, <16 x i16>* %b
|
||||
%ahead = insertelement <16 x i16> undef, i16 %a, i32 0
|
||||
%va = shufflevector <16 x i16> %ahead, <16 x i16> undef, <16 x i32> zeroinitializer
|
||||
%vcc = load <16 x i1>, <16 x i1>* %cc
|
||||
%vsel = select <16 x i1> %vcc, <16 x i16> %va, <16 x i16> %vb
|
||||
store <16 x i16> %vsel, <16 x i16>* %z
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vselect_vi_v16i16(<16 x i16>* %b, <16 x i1>* %cc, <16 x i16>* %z) {
|
||||
; CHECK-LABEL: vselect_vi_v16i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a3, zero, 16
|
||||
; CHECK-NEXT: vsetvli a4, a3, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vle16.v v26, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a3, e8,m1,ta,mu
|
||||
; CHECK-NEXT: vle1.v v0, (a1)
|
||||
; CHECK-NEXT: vsetvli a0, a3, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vmerge.vim v26, v26, 4, v0
|
||||
; CHECK-NEXT: vse16.v v26, (a2)
|
||||
; CHECK-NEXT: ret
|
||||
%vb = load <16 x i16>, <16 x i16>* %b
|
||||
%a = insertelement <16 x i16> undef, i16 4, i32 0
|
||||
%va = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
|
||||
%vcc = load <16 x i1>, <16 x i1>* %cc
|
||||
%vsel = select <16 x i1> %vcc, <16 x i16> %va, <16 x i16> %vb
|
||||
store <16 x i16> %vsel, <16 x i16>* %z
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vselect_vv_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x i1>* %cc, <32 x half>* %z) {
|
||||
; CHECK-LABEL: vselect_vv_v32f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a4, zero, 32
|
||||
; CHECK-NEXT: vsetvli a5, a4, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a0)
|
||||
; CHECK-NEXT: vle16.v v8, (a1)
|
||||
; CHECK-NEXT: vsetvli a0, a4, e8,m2,ta,mu
|
||||
; CHECK-NEXT: vle1.v v0, (a2)
|
||||
; CHECK-NEXT: vsetvli a0, a4, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vmerge.vvm v28, v8, v28, v0
|
||||
; CHECK-NEXT: vse16.v v28, (a3)
|
||||
; CHECK-NEXT: ret
|
||||
%va = load <32 x half>, <32 x half>* %a
|
||||
%vb = load <32 x half>, <32 x half>* %b
|
||||
%vcc = load <32 x i1>, <32 x i1>* %cc
|
||||
%vsel = select <32 x i1> %vcc, <32 x half> %va, <32 x half> %vb
|
||||
store <32 x half> %vsel, <32 x half>* %z
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vselect_vx_v32f16(half %a, <32 x half>* %b, <32 x i1>* %cc, <32 x half>* %z) {
|
||||
; CHECK-LABEL: vselect_vx_v32f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a3, zero, 32
|
||||
; CHECK-NEXT: vsetvli a4, a3, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a3, e8,m2,ta,mu
|
||||
; CHECK-NEXT: vle1.v v0, (a1)
|
||||
; CHECK-NEXT: vsetvli a0, a3, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfmerge.vfm v28, v28, fa0, v0
|
||||
; CHECK-NEXT: vse16.v v28, (a2)
|
||||
; CHECK-NEXT: ret
|
||||
%vb = load <32 x half>, <32 x half>* %b
|
||||
%ahead = insertelement <32 x half> undef, half %a, i32 0
|
||||
%va = shufflevector <32 x half> %ahead, <32 x half> undef, <32 x i32> zeroinitializer
|
||||
%vcc = load <32 x i1>, <32 x i1>* %cc
|
||||
%vsel = select <32 x i1> %vcc, <32 x half> %va, <32 x half> %vb
|
||||
store <32 x half> %vsel, <32 x half>* %z
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vselect_vfpzero_v32f16(<32 x half>* %b, <32 x i1>* %cc, <32 x half>* %z) {
|
||||
; CHECK-LABEL: vselect_vfpzero_v32f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a3, zero, 32
|
||||
; CHECK-NEXT: vsetvli a4, a3, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a3, e8,m2,ta,mu
|
||||
; CHECK-NEXT: vle1.v v0, (a1)
|
||||
; CHECK-NEXT: vsetvli a0, a3, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vmerge.vim v28, v28, 0, v0
|
||||
; CHECK-NEXT: vse16.v v28, (a2)
|
||||
; CHECK-NEXT: ret
|
||||
%vb = load <32 x half>, <32 x half>* %b
|
||||
%a = insertelement <32 x half> undef, half 0.0, i32 0
|
||||
%va = shufflevector <32 x half> %a, <32 x half> undef, <32 x i32> zeroinitializer
|
||||
%vcc = load <32 x i1>, <32 x i1>* %cc
|
||||
%vsel = select <32 x i1> %vcc, <32 x half> %va, <32 x half> %vb
|
||||
store <32 x half> %vsel, <32 x half>* %z
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user