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Add selection DAG nodes for subreg insert/extract. PR1350

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llvm-svn: 40516
This commit is contained in:
Christopher Lamb 2007-07-26 07:34:40 +00:00
parent 2d47a6faec
commit 73c3cd47cc
4 changed files with 35 additions and 2 deletions
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9
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -289,6 +289,15 @@ namespace ISD {
/// elements of the vector are undefined.
SCALAR_TO_VECTOR,
// EXTRACT_SUBREG - This node is used to extract a sub-register value.
// This node takes a superreg and a constant sub-register index as operands.
EXTRACT_SUBREG,
// INSERT_SUBREG - This node is used to insert a sub-register value.
// This node takes a superreg, a subreg value, and a constant sub-register
// index as operands.
INSERT_SUBREG,
// MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
// an unsigned/signed value of type i[2*n], then return the top part.
MULHU, MULHS,

18
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -957,7 +957,23 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
AddLegalizedOperand(SDOperand(Node, i), Tmp1);
}
return Tmp2;
case ISD::EXTRACT_SUBREG: {
Tmp1 = LegalizeOp(Node->getOperand(0));
ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
assert(idx && "Operand must be a constant");
Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
}
break;
case ISD::INSERT_SUBREG: {
Tmp1 = LegalizeOp(Node->getOperand(0));
Tmp2 = LegalizeOp(Node->getOperand(1));
ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
assert(idx && "Operand must be a constant");
Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
}
break;
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");

5
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -3455,7 +3455,10 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::SHL_PARTS: return "shl_parts";
case ISD::SRA_PARTS: return "sra_parts";
case ISD::SRL_PARTS: return "srl_parts";
case ISD::EXTRACT_SUBREG: return "extract_subreg";
case ISD::INSERT_SUBREG: return "insert_subreg";
// Conversion operators.
case ISD::SIGN_EXTEND: return "sign_extend";
case ISD::ZERO_EXTEND: return "zero_extend";

5
lib/Target/TargetSelectionDAG.td
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@ -317,6 +317,11 @@ def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
SDTypeProfile<1, 2, []>>;
def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
SDTypeProfile<1, 3, []>>;
// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
// these internally. Don't reference these directly.