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[MachineVerifier] Verify that a DBG_VALUE has a debug location

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Summary:
Verify that each DBG_VALUE has a debug location. This is required by
LiveDebugValues, and perhaps by other late passes.

There's an exception for tests: lots of tests use a two-operand form of
DBG_VALUE for convenience. There's no reason to prevent that.

This is an extension of D80665, but there's no dependency.

Reviewers: aprantl, jmorse, davide, chrisjackson

Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80670
This commit is contained in:
Vedant Kumar 2020-05-27 15:44:10 -07:00
parent 7f60fb1f6e
commit 73e2a5da53
8 changed files with 50 additions and 27 deletions
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7
lib/CodeGen/MachineVerifier.cpp
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@ -1488,6 +1488,13 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
if (MI->isInlineAsm())
verifyInlineAsm(MI);
// A fully-formed DBG_VALUE must have a location. Ignore partially formed
// DBG_VALUEs: these are convenient to use in tests, but should never get
// generated.
if (MI->isDebugValue() && MI->getNumOperands() == 4)
if (!MI->getDebugLoc())
report("Missing DebugLoc for debug instruction", MI);
// Check the MachineMemOperands for basic consistency.
for (MachineMemOperand *Op : MI->memoperands()) {
if (Op->isLoad() && !MI->mayLoad())

11
test/CodeGen/Hexagon/early-if-debug.mir
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@ -18,7 +18,6 @@
define void @foo() {
ret void
}
!1 = !DIExpression()
...
---
name: foo
@ -40,11 +39,11 @@ body: |
J2_jump %bb.1, implicit-def dead $pc
bb.1:
DBG_VALUE %0, $noreg, !1, !1
DBG_VALUE %0, $noreg, !1, !1
DBG_VALUE %0, $noreg, !1, !1
DBG_VALUE %0, $noreg, !1, !1
DBG_VALUE %0, $noreg, !1, !1
DBG_VALUE %0, $noreg
DBG_VALUE %0, $noreg
DBG_VALUE %0, $noreg
DBG_VALUE %0, $noreg
DBG_VALUE %0, $noreg
%3 = A2_tfrsi 321
bb.2:

19
test/CodeGen/MIR/Generic/dbg-value-missing-loc.mir Normal file
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@ -0,0 +1,19 @@
# RUN: not --crash llc -run-pass machineverifier -o - %s 2>&1 | FileCheck %s
# CHECK: Bad machine code: Missing DebugLoc for debug instruction
# CHECK: - instruction: DBG_VALUE 1, 2, 3, 4
--- |
define i32 @foo() {
entry:
ret i32 0
}
...
---
name: foo
body: |
bb.0.entry:
DBG_VALUE 1, 2, 3, 4
...

12
test/CodeGen/MIR/X86/instructions-debug-location.mir
View File

@ -99,12 +99,12 @@ body: |
liveins: $edi
%0 = COPY $edi
; CHECK: DBG_VALUE $noreg, i32 0, !DIExpression(), !12
; CHECK-NEXT: DBG_VALUE $noreg, i64 -22, !DIExpression(), !12
; CHECK-NEXT: DBG_VALUE $noreg, i128 123492148938512984928424384934328985928, !DIExpression(), !12
DBG_VALUE _, i32 0, !DIExpression(), !13
DBG_VALUE _, i64 -22, !DIExpression(), !13
DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !13
; CHECK: DBG_VALUE $noreg, i32 0, !11, !DIExpression()
; CHECK-NEXT: DBG_VALUE $noreg, i64 -22, !11, !DIExpression()
; CHECK-NEXT: DBG_VALUE $noreg, i128 123492148938512984928424384934328985928, !11, !DIExpression()
DBG_VALUE _, i32 0, !12, !DIExpression(), debug-location !13
DBG_VALUE _, i64 -22, !12, !DIExpression(), debug-location !13
DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !DIExpression(), debug-location !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
$eax = COPY %0
RETQ $eax

2
test/CodeGen/MIR/X86/metadata-operands.mir
View File

@ -53,7 +53,7 @@ body: |
; CHECK: %0:gr32 = COPY $edi
; CHECK-NEXT: DBG_VALUE $noreg, 0, !11, !DIExpression()
%0 = COPY $edi
DBG_VALUE _, 0, !12, !DIExpression()
DBG_VALUE _, 0, !12, !DIExpression(), debug-location !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
$eax = COPY %0
RETQ $eax

19
test/CodeGen/RISCV/select-optimize-multiple.mir
View File

@ -13,7 +13,6 @@
define void @cmov_interleaved_debug_value() {
ret void
}
!1 = !DIExpression()
...
---
# Here we have a sequence of select instructions with a non-select instruction
@ -139,14 +138,14 @@ body: |
; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
; RV32I: DBG_VALUE [[ADDI]], $noreg, !DIExpression(), !DIExpression()
; RV32I: DBG_VALUE [[ADDI]], $noreg
; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
; RV32I: .1:
; RV32I: .2:
; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV32I: DBG_VALUE [[PHI]], $noreg, !DIExpression(), !DIExpression()
; RV32I: DBG_VALUE [[PHI1]], $noreg, !DIExpression(), !DIExpression()
; RV32I: DBG_VALUE [[PHI]], $noreg
; RV32I: DBG_VALUE [[PHI1]], $noreg
; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV32I: $x10 = COPY [[ADD]]
; RV32I: PseudoRET implicit $x10
@ -160,14 +159,14 @@ body: |
; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
; RV64I: DBG_VALUE [[ADDI]], $noreg, !DIExpression(), !DIExpression()
; RV64I: DBG_VALUE [[ADDI]], $noreg
; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
; RV64I: .1:
; RV64I: .2:
; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV64I: DBG_VALUE [[PHI]], $noreg, !DIExpression(), !DIExpression()
; RV64I: DBG_VALUE [[PHI1]], $noreg, !DIExpression(), !DIExpression()
; RV64I: DBG_VALUE [[PHI]], $noreg
; RV64I: DBG_VALUE [[PHI1]], $noreg
; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV64I: $x10 = COPY [[ADD]]
; RV64I: PseudoRET implicit $x10
@ -178,11 +177,11 @@ body: |
%5:gpr = ANDI %0, 1
%6:gpr = COPY $x0
%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
DBG_VALUE %7, $noreg, !1, !1
DBG_VALUE %7, $noreg
%8:gpr = ADDI %0, 1
DBG_VALUE %8, $noreg, !1, !1
DBG_VALUE %8, $noreg
%9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
DBG_VALUE %9, $noreg, !1, !1
DBG_VALUE %9, $noreg
%10:gpr = ADD %7, killed %9
$x10 = COPY %10
PseudoRET implicit $x10

3
test/CodeGen/X86/machine-cp-debug.mir
View File

@ -9,7 +9,6 @@
define void @fred() {
ret void
}
!1 = !DIExpression()
...
---
@ -19,5 +18,5 @@ body: |
bb.0:
liveins: $eax
$ebx = COPY $eax
DBG_VALUE $ebx, _, !1, !1
DBG_VALUE $ebx, _
...

4
test/CodeGen/X86/pr38952.mir
View File

@ -72,10 +72,10 @@ body: |
; Test that the DBG_VALUE on ebx below is sunk with the def of ebx, despite
; not being adjacent to the def, see PR38952
DBG_VALUE $edi, $noreg, !21, !DIExpression()
DBG_VALUE $edi, $noreg
renamable $ebx = COPY $edi
renamable $eax = MOV32r0 implicit-def dead $eflags
DBG_VALUE $ebx, $noreg, !21, !DIExpression()
DBG_VALUE $ebx, $noreg
CMP32ri $edi, 255, implicit-def $eflags
JCC_1 %bb.2, 15, implicit killed $eflags
JMP_1 %bb.1