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CodeGen: Use MachineInstr& in RegisterCoalescer, NFC
Remove a few more implicit iterator to pointer conversions by preferring MachineInstr&. llvm-svn: 274363
This commit is contained in:
Duncan P. N. Exon Smith
parent
e0079e069e
commit
73e9436c33
@ -954,8 +954,8 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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MachineBasicBlock::iterator MII =
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std::next(MachineBasicBlock::iterator(CopyMI));
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TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, *DefMI, *TRI);
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MachineInstr *NewMI = std::prev(MII);
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NewMI->setDebugLoc(DL);
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MachineInstr &NewMI = *std::prev(MII);
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NewMI.setDebugLoc(DL);
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// In a situation like the following:
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// %vreg0:subreg = instr ; DefMI, subreg = DstIdx
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@ -964,7 +964,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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// %vreg1 = instr
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const TargetRegisterClass *NewRC = CP.getNewRC();
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if (DstIdx != 0) {
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MachineOperand &DefMO = NewMI->getOperand(0);
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MachineOperand &DefMO = NewMI.getOperand(0);
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if (DefMO.getSubReg() == DstIdx) {
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assert(SrcIdx == 0 && CP.isFlipped()
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&& "Shouldn't have SrcIdx+DstIdx at this point");
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@ -996,7 +996,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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}
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}
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LIS->ReplaceMachineInstrInMaps(*CopyMI, *NewMI);
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LIS->ReplaceMachineInstrInMaps(*CopyMI, NewMI);
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CopyMI->eraseFromParent();
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ErasedInstrs.insert(CopyMI);
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@ -1004,9 +1004,10 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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// We need to remember these so we can add intervals once we insert
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// NewMI into SlotIndexes.
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SmallVector<unsigned, 4> NewMIImplDefs;
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for (unsigned i = NewMI->getDesc().getNumOperands(),
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e = NewMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = NewMI->getOperand(i);
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for (unsigned i = NewMI.getDesc().getNumOperands(),
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e = NewMI.getNumOperands();
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i != e; ++i) {
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MachineOperand &MO = NewMI.getOperand(i);
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if (MO.isReg() && MO.isDef()) {
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assert(MO.isImplicit() && MO.isDead() &&
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TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
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@ -1015,7 +1016,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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}
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if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
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unsigned NewIdx = NewMI->getOperand(0).getSubReg();
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unsigned NewIdx = NewMI.getOperand(0).getSubReg();
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if (DefRC != nullptr) {
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if (NewIdx)
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@ -1033,7 +1034,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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// Update machine operands and add flags.
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updateRegDefsUses(DstReg, DstReg, DstIdx);
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NewMI->getOperand(0).setSubReg(NewIdx);
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NewMI.getOperand(0).setSubReg(NewIdx);
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// Add dead subregister definitions if we are defining the whole register
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// but only part of it is live.
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// This could happen if the rematerialization instruction is rematerializing
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@ -1049,8 +1050,9 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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// at this point for the part that wasn't defined before we could have
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// subranges missing the definition.
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if (NewIdx == 0 && DstInt.hasSubRanges()) {
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SlotIndex CurrIdx = LIS->getInstructionIndex(*NewMI);
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SlotIndex DefIndex = CurrIdx.getRegSlot(NewMI->getOperand(0).isEarlyClobber());
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SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
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SlotIndex DefIndex =
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CurrIdx.getRegSlot(NewMI.getOperand(0).isEarlyClobber());
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LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(DstReg);
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VNInfo::Allocator& Alloc = LIS->getVNInfoAllocator();
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for (LiveInterval::SubRange &SR : DstInt.subranges()) {
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@ -1063,16 +1065,14 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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SR->createDeadDef(DefIndex, Alloc);
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}
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}
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} else if (NewMI->getOperand(0).getReg() != CopyDstReg) {
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} else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
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// The New instruction may be defining a sub-register of what's actually
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// been asked for. If so it must implicitly define the whole thing.
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assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
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"Only expect virtual or physical registers in remat");
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NewMI->getOperand(0).setIsDead(true);
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NewMI->addOperand(MachineOperand::CreateReg(CopyDstReg,
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true /*IsDef*/,
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true /*IsImp*/,
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false /*IsKill*/));
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NewMI.getOperand(0).setIsDead(true);
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NewMI.addOperand(MachineOperand::CreateReg(
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CopyDstReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
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// Record small dead def live-ranges for all the subregisters
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// of the destination register.
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// Otherwise, variables that live through may miss some
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@ -1089,21 +1089,21 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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// vreg1 will see the inteferences with CL but not with CH since
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// no live-ranges would have been created for ECX.
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// Fix that!
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SlotIndex NewMIIdx = LIS->getInstructionIndex(*NewMI);
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for (MCRegUnitIterator Units(NewMI->getOperand(0).getReg(), TRI);
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SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
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for (MCRegUnitIterator Units(NewMI.getOperand(0).getReg(), TRI);
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Units.isValid(); ++Units)
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if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
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LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
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}
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if (NewMI->getOperand(0).getSubReg())
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NewMI->getOperand(0).setIsUndef();
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if (NewMI.getOperand(0).getSubReg())
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NewMI.getOperand(0).setIsUndef();
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// Transfer over implicit operands to the rematerialized instruction.
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for (MachineOperand &MO : ImplicitOps)
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NewMI->addOperand(MO);
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NewMI.addOperand(MO);
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SlotIndex NewMIIdx = LIS->getInstructionIndex(*NewMI);
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SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
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for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
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unsigned Reg = NewMIImplDefs[i];
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for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
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@ -1111,7 +1111,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
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}
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DEBUG(dbgs() << "Remat: " << *NewMI);
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DEBUG(dbgs() << "Remat: " << NewMI);
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++NumReMats;
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// The source interval can become smaller because we removed a use.
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@ -1849,7 +1849,7 @@ class JoinVals {
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/// Return true if MI uses any of the given Lanes from Reg.
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/// This does not include partial redefinitions of Reg.
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bool usesLanes(const MachineInstr *MI, unsigned, unsigned, LaneBitmask) const;
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bool usesLanes(const MachineInstr &MI, unsigned, unsigned, LaneBitmask) const;
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/// Determine if ValNo is a copy of a value number in LR or Other.LR that will
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/// be pruned:
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@ -2293,11 +2293,11 @@ taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
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return true;
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}
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bool JoinVals::usesLanes(const MachineInstr *MI, unsigned Reg, unsigned SubIdx,
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bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx,
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LaneBitmask Lanes) const {
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if (MI->isDebugValue())
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if (MI.isDebugValue())
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return false;
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for (const MachineOperand &MO : MI->operands()) {
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
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continue;
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if (!MO.readsReg())
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@ -2352,7 +2352,7 @@ bool JoinVals::resolveConflicts(JoinVals &Other) {
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unsigned TaintNum = 0;
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for(;;) {
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assert(MI != MBB->end() && "Bad LastMI");
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if (usesLanes(MI, Other.Reg, Other.SubIdx, TaintedLanes)) {
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if (usesLanes(*MI, Other.Reg, Other.SubIdx, TaintedLanes)) {
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DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
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return false;
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}
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@ -2912,16 +2912,15 @@ RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
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}
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else {
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SmallVector<MachineInstr*, 2> Terminals;
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for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
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MII != E; ++MII)
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if (MII->isCopyLike()) {
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if (applyTerminalRule(*MII))
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Terminals.push_back(&(*MII));
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for (MachineInstr &MII : *MBB)
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if (MII.isCopyLike()) {
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if (applyTerminalRule(MII))
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Terminals.push_back(&MII);
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else
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WorkList.push_back(MII);
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}
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// Append the copies evicted by the terminal rule at the end of the list.
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WorkList.append(Terminals.begin(), Terminals.end());
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WorkList.push_back(&MII);
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}
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// Append the copies evicted by the terminal rule at the end of the list.
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WorkList.append(Terminals.begin(), Terminals.end());
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}
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// Try coalescing the collected copies immediately, and remove the nulls.
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// This prevents the WorkList from getting too large since most copies are
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