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AMDGPU: Cleanup sra test
llvm-svn: 258086
This commit is contained in:
Matt Arsenault
parent
1478312f09
commit
7414572d7c
@ -1,213 +1,256 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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;EG-LABEL: {{^}}ashr_v2i32:
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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declare i32 @llvm.r600.read.tidig.x() #0
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;SI-LABEL: {{^}}ashr_v2i32:
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; FUNC-LABEL: {{^}}ashr_v2i32:
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; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI-LABEL: {{^}}ashr_v2i32:
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%a = load <2 x i32>, <2 x i32> addrspace(1)* %in
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%b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
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%result = ashr <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_v4i32:
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; FUNC-LABEL: {{^}}ashr_v4i32:
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; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-LABEL: {{^}}ashr_v4i32:
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI-LABEL: {{^}}ashr_v4i32:
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%a = load <4 x i32>, <4 x i32> addrspace(1)* %in
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%b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
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%result = ashr <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_i64:
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;EG: ASHR
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; FUNC-LABEL: {{^}}s_ashr_i64:
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; GCN: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
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;SI-LABEL: {{^}}ashr_i64:
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;SI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
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;VI-LABEL: {{^}}ashr_i64:
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;VI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
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define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) {
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; EG: ASHR
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define void @s_ashr_i64(i64 addrspace(1)* %out, i32 %in) {
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entry:
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%0 = sext i32 %in to i64
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%1 = ashr i64 %0, 8
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store i64 %1, i64 addrspace(1)* %out
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%in.ext = sext i32 %in to i64
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%ashr = ashr i64 %in.ext, 8
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store i64 %ashr, i64 addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_i64_2:
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;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
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;EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
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;EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
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;EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}}
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;EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|PV.[XYZW]|[[SHIFT]]}}
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;EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
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;EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
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;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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; FUNC-LABEL: {{^}}ashr_i64_2:
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; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI-LABEL: {{^}}ashr_i64_2:
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;VI-LABEL: {{^}}ashr_i64_2:
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
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; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
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; EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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; EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
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; EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
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; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}}
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; EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|PV.[XYZW]|[[SHIFT]]}}
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; EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
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; EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
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; EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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entry:
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%b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
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%a = load i64, i64 addrspace(1) * %in
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%b = load i64, i64 addrspace(1) * %b_ptr
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%a = load i64, i64 addrspace(1)* %in
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%b = load i64, i64 addrspace(1)* %b_ptr
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%result = ashr i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_v2i64:
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: ASHR {{.*}}, [[SHA]]
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;EG-DAG: ASHR {{.*}}, [[SHB]]
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;EG-DAG: LSHR {{.*}}, [[SHA]]
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;EG-DAG: LSHR {{.*}}, [[SHB]]
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;EG-DAG: OR_INT
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;EG-DAG: OR_INT
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ASHR
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;EG-DAG: ASHR
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;EG-DAG: ASHR {{.*}}, literal
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;EG-DAG: ASHR {{.*}}, literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;SI-LABEL: {{^}}ashr_v2i64:
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;VI-LABEL: {{^}}ashr_v2i64:
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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; FUNC-LABEL: {{^}}ashr_v2i64:
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; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
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; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
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; EG-DAG: LSHL {{.*}}, 1
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; EG-DAG: LSHL {{.*}}, 1
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; EG-DAG: ASHR {{.*}}, [[SHA]]
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; EG-DAG: ASHR {{.*}}, [[SHB]]
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; EG-DAG: LSHR {{.*}}, [[SHA]]
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; EG-DAG: LSHR {{.*}}, [[SHB]]
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; EG-DAG: OR_INT
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; EG-DAG: OR_INT
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; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
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; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
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; EG-DAG: ASHR
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; EG-DAG: ASHR
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; EG-DAG: ASHR {{.*}}, literal
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; EG-DAG: ASHR {{.*}}, literal
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; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
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; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
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%a = load <2 x i64>, <2 x i64> addrspace(1) * %in
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%b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr
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%a = load <2 x i64>, <2 x i64> addrspace(1)* %in
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%b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
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%result = ashr <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_v4i64:
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHC]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHD]]
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: LSHL {{.*}}, 1
|
||||
;EG-DAG: ASHR {{.*}}, [[SHA]]
|
||||
;EG-DAG: ASHR {{.*}}, [[SHB]]
|
||||
;EG-DAG: ASHR {{.*}}, [[SHC]]
|
||||
;EG-DAG: ASHR {{.*}}, [[SHD]]
|
||||
;EG-DAG: LSHR {{.*}}, [[SHA]]
|
||||
;EG-DAG: LSHR {{.*}}, [[SHB]]
|
||||
;EG-DAG: LSHR {{.*}}, [[SHA]]
|
||||
;EG-DAG: LSHR {{.*}}, [[SHB]]
|
||||
;EG-DAG: OR_INT
|
||||
;EG-DAG: OR_INT
|
||||
;EG-DAG: OR_INT
|
||||
;EG-DAG: OR_INT
|
||||
;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
;EG-DAG: ASHR
|
||||
;EG-DAG: ASHR
|
||||
;EG-DAG: ASHR
|
||||
;EG-DAG: ASHR
|
||||
;EG-DAG: ASHR {{.*}}, literal
|
||||
;EG-DAG: ASHR {{.*}}, literal
|
||||
;EG-DAG: ASHR {{.*}}, literal
|
||||
;EG-DAG: ASHR {{.*}}, literal
|
||||
;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
|
||||
;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
|
||||
;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
|
||||
;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
|
||||
;EG-DAG: CNDE_INT
|
||||
;EG-DAG: CNDE_INT
|
||||
;EG-DAG: CNDE_INT
|
||||
;EG-DAG: CNDE_INT
|
||||
;EG-DAG: CNDE_INT
|
||||
;EG-DAG: CNDE_INT
|
||||
;EG-DAG: CNDE_INT
|
||||
;EG-DAG: CNDE_INT
|
||||
; FIXME: Broken on r600
|
||||
; XFUNC-LABEL: {{^}}s_ashr_v2i64:
|
||||
; XGCN: s_ashr_i64 {{s\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], s[0-9]+}}
|
||||
; XGCN: s_ashr_i64 {{s\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], s[0-9]+}}
|
||||
; define void @s_ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in, <2 x i64> %a, <2 x i64> %b) {
|
||||
; %result = ashr <2 x i64> %a, %b
|
||||
; store <2 x i64> %result, <2 x i64> addrspace(1)* %out
|
||||
; ret void
|
||||
; }
|
||||
|
||||
;SI-LABEL: {{^}}ashr_v4i64:
|
||||
;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
; FUNC-LABEL: {{^}}ashr_v4i64:
|
||||
; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
|
||||
;VI-LABEL: {{^}}ashr_v4i64:
|
||||
;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
||||
;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
||||
;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
||||
;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
||||
; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
||||
; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
||||
; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
||||
; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
||||
|
||||
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
|
||||
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
|
||||
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
|
||||
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
|
||||
; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
|
||||
; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
|
||||
; EG-DAG: LSHL {{\*? *}}[[COMPSHC]]
|
||||
; EG-DAG: LSHL {{\*? *}}[[COMPSHD]]
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: ASHR {{.*}}, [[SHA]]
|
||||
; EG-DAG: ASHR {{.*}}, [[SHB]]
|
||||
; EG-DAG: ASHR {{.*}}, [[SHC]]
|
||||
; EG-DAG: ASHR {{.*}}, [[SHD]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHA]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHB]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHA]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHB]]
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: ASHR {{.*}}, literal
|
||||
; EG-DAG: ASHR {{.*}}, literal
|
||||
; EG-DAG: ASHR {{.*}}, literal
|
||||
; EG-DAG: ASHR {{.*}}, literal
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
|
||||
%a = load <4 x i64>, <4 x i64> addrspace(1) * %in
|
||||
%b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr
|
||||
%a = load <4 x i64>, <4 x i64> addrspace(1)* %in
|
||||
%b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
|
||||
%result = ashr <4 x i64> %a, %b
|
||||
store <4 x i64> %result, <4 x i64> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_ashr_32_i64:
|
||||
; GCN: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
|
||||
; GCN: s_ashr_i64 [[SHIFT:s\[[0-9]+:[0-9]+\]]], [[VAL]], 32
|
||||
; GCN: s_add_u32
|
||||
; GCN: s_addc_u32
|
||||
define void @s_ashr_32_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
|
||||
%result = ashr i64 %a, 32
|
||||
%add = add i64 %result, %b
|
||||
store i64 %add, i64 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_ashr_32_i64:
|
||||
; GCN: {{buffer|flat}}_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
|
||||
; SI: v_ashr_i64 [[SHIFT:v\[[0-9]+:[0-9]+\]]], [[VAL]], 32
|
||||
; VI: v_ashrrev_i64 [[SHIFT:v\[[0-9]+:[0-9]+\]]], 32, [[VAL]]
|
||||
; GCN: {{buffer|flat}}_store_dwordx2 [[SHIFT]]
|
||||
define void @v_ashr_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
|
||||
%gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
||||
%a = load i64, i64 addrspace(1)* %gep.in
|
||||
%result = ashr i64 %a, 32
|
||||
store i64 %result, i64 addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_ashr_63_i64:
|
||||
; GCN-DAG: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
|
||||
; GCN: s_ashr_i64 [[SHIFT:s\[[0-9]+:[0-9]+\]]], [[VAL]], 63
|
||||
; GCN: s_add_u32
|
||||
define void @s_ashr_63_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
|
||||
%result = ashr i64 %a, 63
|
||||
%add = add i64 %result, %b
|
||||
store i64 %add, i64 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_ashr_63_i64:
|
||||
; GCN-DAG: {{buffer|flat}}_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
|
||||
; SI: v_ashr_i64 [[SHIFT:v\[[0-9]+:[0-9]+\]]], [[VAL]], 63
|
||||
; VI: v_ashrrev_i64 [[SHIFT:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]]
|
||||
; GCN: {{buffer|flat}}_store_dwordx2 [[SHIFT]]
|
||||
define void @v_ashr_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
|
||||
%gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
||||
%a = load i64, i64 addrspace(1)* %gep.in
|
||||
%result = ashr i64 %a, 63
|
||||
store i64 %result, i64 addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user