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[AMDGPU] Disassembler: fix s_buffer_store_dword instructions
Summary: s_buffer_store_dword instructions sdata operand was called sdst in encoding. This caused disassembler to fail. Reviewers: tstellarAMD, vpykhtin, artem.tamazov Subscribers: arsenm, nhaehnle, rampitec Differential Revision: https://reviews.llvm.org/D27100 llvm-svn: 288657
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@ -394,16 +394,24 @@ multiclass SM_Real_Loads_vi<bits<8> op, string ps,
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}
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}
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class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
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// encoding
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bits<7> sdata;
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let sdst = ?;
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let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
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}
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multiclass SM_Real_Stores_vi<bits<8> op, string ps,
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SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
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SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
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// FIXME: The operand name $offset is inconsistent with $soff used
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// in the pseudo
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def _IMM_vi : SMEM_Real_vi <op, immPs> {
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def _IMM_vi : SMEM_Real_Store_vi <op, immPs> {
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let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
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}
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def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
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def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> {
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let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
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}
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}
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@ -427,6 +435,7 @@ defm S_BUFFER_STORE_DWORD : SM_Real_Stores_vi <0x18, "S_BUFFER_STORE_DWORD">;
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defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_vi <0x19, "S_BUFFER_STORE_DWORDX2">;
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defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_vi <0x1a, "S_BUFFER_STORE_DWORDX4">;
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// These instructions use same encoding
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def S_DCACHE_INV_vi : SMEM_Real_vi <0x20, S_DCACHE_INV>;
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def S_DCACHE_WB_vi : SMEM_Real_vi <0x21, S_DCACHE_WB>;
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def S_DCACHE_INV_VOL_vi : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>;
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@ -1,35 +1,38 @@
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s
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// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOSI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOSICI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=NOSICI %s
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s_dcache_wb
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// VI: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
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// NOSI: error: instruction not supported on this GPU
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// NOSICI: error: instruction not supported on this GPU
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s_dcache_wb_vol
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// VI: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
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// NOSI: error: instruction not supported on this GPU
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// NOSICI: error: instruction not supported on this GPU
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s_memrealtime s[4:5]
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// VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
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// NOSI: error: instruction not supported on this GPU
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// NOSICI: error: instruction not supported on this GPU
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// FIXME: Should error about instruction on GPU
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s_store_dword s1, s[2:3], 0xfc
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// VI: s_store_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x42,0xc0,0xfc,0x00,0x00,0x00]
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// NOSI: error: instruction not supported on this GPU
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// NOSICI: error: instruction not supported on this GPU
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s_store_dword s1, s[2:3], 0xfc glc
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// VI: s_store_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x43,0xc0,0xfc,0x00,0x00,0x00]
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// NOSI: error: invalid operand for instruction
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// NOSICI: error: invalid operand for instruction
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s_store_dword s1, s[2:3], s4
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// VI: s_store_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x40,0xc0,0x04,0x00,0x00,0x00]
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// NOSI: error: instruction not supported on this GPU
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// NOSICI: error: instruction not supported on this GPU
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s_store_dword s1, s[2:3], s4 glc
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// VI: s_store_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x41,0xc0,0x04,0x00,0x00,0x00]
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// NOSI: error: invalid operand for instruction
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// NOSICI: error: invalid operand for instruction
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// FIXME: Should error on SI instead of silently ignoring glc
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s_load_dword s1, s[2:3], 0xfc glc
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@ -37,3 +40,27 @@ s_load_dword s1, s[2:3], 0xfc glc
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s_load_dword s1, s[2:3], s4 glc
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// VI: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xc0,0x04,0x00,0x00,0x00]
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s_buffer_store_dword s10, s[92:95], m0
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// VI: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xc0,0x7c,0x00,0x00,0x00]
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// NOSICI: error: instruction not supported on this GPU
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s_buffer_store_dwordx2 s[10:11], s[92:95], m0
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// VI: s_buffer_store_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x64,0xc0,0x7c,0x00,0x00,0x00]
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// NOSICI: error: instruction not supported on this GPU
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s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc
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// VI: s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x69,0xc0,0x7c,0x00,0x00,0x00]
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// NOSICI: error: invalid operand for instruction
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s_buffer_load_dword s10, s[92:95], m0
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// VI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xc0,0x7c,0x00,0x00,0x00]
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// SICI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0x7c,0x5c,0x05,0xc2]
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s_buffer_load_dwordx2 s[10:11], s[92:95], m0
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// VI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
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// SICI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0x7c,0x5c,0x45,0xc2]
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// FIXME: Should error on SI instead of silently ignoring glc
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s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc
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// VI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]
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@ -8,3 +8,39 @@
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# VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
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0x00 0x01 0x94 0xc0 0x00 0x00 0x00 0x00
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# VI: s_store_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x42,0xc0,0xfc,0x00,0x00,0x00]
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0x41 0x00 0x42 0xc0 0xfc 0x00 0x00 0x00
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# VI: s_store_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x43,0xc0,0xfc,0x00,0x00,0x00]
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0x41 0x00 0x43 0xc0 0xfc 0x00 0x00 0x00
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# VI: s_store_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x40,0xc0,0x04,0x00,0x00,0x00]
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0x41 0x00 0x40 0xc0 0x04 0x00 0x00 0x00
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# VI: s_store_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x41,0xc0,0x04,0x00,0x00,0x00]
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0x41 0x00 0x41 0xc0 0x04 0x00 0x00 0x00
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# VI: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x03,0xc0,0xfc,0x00,0x00,0x00]
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0x41 0x00 0x03 0xc0 0xfc 0x00 0x00 0x00
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# VI: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xc0,0x04,0x00,0x00,0x00]
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0x41 0x00 0x01 0xc0 0x04 0x00 0x00 0x00
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# VI: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xc0,0x7c,0x00,0x00,0x00]
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0xae 0x02 0x60 0xc0 0x7c 0x00 0x00 0x00
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# VI: s_buffer_store_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x64,0xc0,0x7c,0x00,0x00,0x00]
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0xae 0x02 0x64 0xc0 0x7c 0x00 0x00 0x00
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# VI: s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x69,0xc0,0x7c,0x00,0x00,0x00]
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0x2e 0x02 0x69 0xc0 0x7c 0x00 0x00 0x00
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# VI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xc0,0x7c,0x00,0x00,0x00]
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0xae 0x02 0x20 0xc0 0x7c 0x00 0x00 0x00
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# VI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
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0xae 0x02 0x24 0xc0 0x7c 0x00 0x00 0x00
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# VI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]
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0x2e 0x02 0x29 0xc0 0x7c 0x00 0x00 0x00
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