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Revert "Revert r339977: [GISel]: Add Opcodes for a few LLVM Intrinsics"

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This reverts commit 7debc334e6421bb5251ef8f18e97166dfc7dd787.

I missed updating legalizer-info-validation.mir as I had assertions
turned off in my build and that specific test requires asserts. Fixed it
now.

llvm-svn: 340197
This commit is contained in:
Aditya Nandakumar 2018-08-20 18:43:19 +00:00
parent 4d848ac04b
commit 7515ede575
5 changed files with 57 additions and 0 deletions
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6
include/llvm/Support/TargetOpcodes.def
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@ -268,6 +268,12 @@ HANDLE_TARGET_OPCODE(G_INTTOPTR)
/// COPY is the relevant instruction.
HANDLE_TARGET_OPCODE(G_BITCAST)
/// INTRINSIC trunc intrinsic.
HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC)
/// INTRINSIC round intrinsic.
HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)
/// Generic load (including anyext load)
HANDLE_TARGET_OPCODE(G_LOAD)

15
include/llvm/Target/GenericOpcodes.td
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@ -512,6 +512,21 @@ def G_FLOG2 : GenericInstruction {
let hasSideEffects = 0;
}
//------------------------------------------------------------------------------
// Opcodes for LLVM Intrinsics
//------------------------------------------------------------------------------
def G_INTRINSIC_TRUNC : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
let hasSideEffects = 0;
}
def G_INTRINSIC_ROUND : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
let hasSideEffects = 0;
}
//------------------------------------------------------------------------------
// Memory ops
//------------------------------------------------------------------------------

10
lib/CodeGen/GlobalISel/IRTranslator.cpp
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@ -861,6 +861,16 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::trunc:
MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC)
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::round:
MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND)
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::fma:
MIRBuilder.buildInstr(TargetOpcode::G_FMA)
.addDef(getOrCreateVReg(CI))

20
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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@ -1408,6 +1408,26 @@ define float @test_fabs_intrin(float %a) {
ret float %res
}
declare float @llvm.trunc.f32(float)
define float @test_intrinsic_trunc(float %a) {
; CHECK-LABEL: name: test_intrinsic_trunc
; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call float @llvm.trunc.f32(float %a)
ret float %res
}
declare float @llvm.round.f32(float)
define float @test_intrinsic_round(float %a) {
; CHECK-LABEL: name: test_intrinsic_round
; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call float @llvm.round.f32(float %a)
ret float %res
}
declare i32 @llvm.ctlz.i32(i32, i1)
define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef

6
test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
View File

@ -78,6 +78,12 @@
# DEBUG-NEXT: G_BITCAST (opcode {{[0-9]+}}): 2 type indices
# DEBUG: .. the first uncovered type index: 2, OK
#
# DEBUG-NEXT: G_INTRINSIC_TRUNC (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. type index coverage check SKIPPED: no rules defined
#
# DEBUG-NEXT: G_INTRINSIC_ROUND (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. type index coverage check SKIPPED: no rules defined
#
# DEBUG-NEXT: G_LOAD (opcode {{[0-9]+}}): 2 type indices
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
#