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Simplify the fast-patch interval spilling by using MachineRegisterInfo::reg_iterator.
llvm-svn: 54930
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@ -1618,83 +1618,61 @@ addIntervalsForSpillsFast(const LiveInterval &li,
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const TargetRegisterClass* rc = mri_->getRegClass(li.reg);
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for (LiveInterval::Ranges::const_iterator
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i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
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unsigned index = getBaseIndex(i->start);
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unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
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for (; index != end; index += InstrSlots::NUM) {
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// skip deleted instructions
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while (index != end && !getInstructionFromIndex(index))
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index += InstrSlots::NUM;
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if (index == end) break;
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DenseMap<MachineInstr*, unsigned> VRegMap;
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DenseMap<MachineInstr*, VNInfo*> VNMap;
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MachineInstr *MI = getInstructionFromIndex(index);
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for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
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RE = mri_->reg_end(); RI != RE; ) {
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// Create a new virtual register for the spill interval.
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MachineOperand& MO = RI.getOperand();
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unsigned NewVReg = 0;
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if (!VRegMap.count(MO.getParent()))
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VRegMap[MO.getParent()] = NewVReg = mri_->createVirtualRegister(rc);
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else
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NewVReg = VRegMap[MO.getParent()];
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// Increment iterator to avoid invalidation.
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++RI;
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MO.setReg(NewVReg);
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for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
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MachineOperand& mop = MI->getOperand(i);
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if (mop.isRegister() && mop.getReg() == li.reg) {
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// Create a new virtual register for the spill interval.
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unsigned NewVReg = mri_->createVirtualRegister(rc);
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// Scan all of the operands of this instruction rewriting operands
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// to use NewVReg instead of li.reg as appropriate. We do this for
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// two reasons:
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//
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// 1. If the instr reads the same spilled vreg multiple times, we
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// want to reuse the NewVReg.
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// 2. If the instr is a two-addr instruction, we are required to
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// keep the src/dst regs pinned.
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//
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// Keep track of whether we replace a use and/or def so that we can
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// create the spill interval with the appropriate range.
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mop.setReg(NewVReg);
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bool HasUse = mop.isUse();
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bool HasDef = mop.isDef();
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for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
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if (MI->getOperand(j).isReg() &&
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MI->getOperand(j).getReg() == li.reg) {
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MI->getOperand(j).setReg(NewVReg);
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HasUse |= MI->getOperand(j).isUse();
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HasDef |= MI->getOperand(j).isDef();
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}
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}
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// create a new register for this spill
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vrm.grow();
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vrm.assignVirt2StackSlot(NewVReg, slot);
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LiveInterval &nI = getOrCreateInterval(NewVReg);
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assert(nI.empty());
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// create a new register for this spill
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vrm.grow();
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vrm.assignVirt2StackSlot(NewVReg, slot);
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LiveInterval &nI = getOrCreateInterval(NewVReg);
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assert(nI.empty());
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// the spill weight is now infinity as it
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// cannot be spilled again
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nI.weight = HUGE_VALF;
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// the spill weight is now infinity as it
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// cannot be spilled again
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nI.weight = HUGE_VALF;
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if (HasUse) {
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LiveRange LR(getLoadIndex(index), getUseIndex(index),
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nI.getNextValue(~0U, 0, getVNInfoAllocator()));
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DOUT << " +" << LR;
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nI.addRange(LR);
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}
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if (HasDef) {
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LiveRange LR(getDefIndex(index), getStoreIndex(index),
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nI.getNextValue(~0U, 0, getVNInfoAllocator()));
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DOUT << " +" << LR;
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nI.addRange(LR);
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}
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added.push_back(&nI);
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// update live variables if it is available
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if (lv_)
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lv_->addVirtualRegisterKilled(NewVReg, MI);
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DOUT << "\t\t\t\tadded new interval: ";
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DEBUG(nI.dump());
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DOUT << '\n';
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}
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}
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unsigned index = getInstructionIndex(MO.getParent());
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bool HasUse = MO.isUse();
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bool HasDef = MO.isDef();
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if (!VNMap.count(MO.getParent()))
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VNMap[MO.getParent()] = nI.getNextValue(~0U, 0, getVNInfoAllocator());
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if (HasUse) {
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LiveRange LR(getLoadIndex(index), getUseIndex(index),
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VNMap[MO.getParent()]);
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DOUT << " +" << LR;
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nI.addRange(LR);
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}
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if (HasDef) {
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LiveRange LR(getDefIndex(index), getStoreIndex(index),
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VNMap[MO.getParent()]);
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DOUT << " +" << LR;
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nI.addRange(LR);
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}
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added.push_back(&nI);
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// update live variables if it is available
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if (lv_)
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lv_->addVirtualRegisterKilled(NewVReg, MO.getParent());
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DOUT << "\t\t\t\tadded new interval: ";
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DEBUG(nI.dump());
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DOUT << '\n';
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}
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SSWeight = HUGE_VALF;
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