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AMDGPU: Check MRI for callee saved regs instead of TRI
This should the same, but MRI does allow dynamically changing the CSR set, although currently not used. llvm-svn: 364425
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@ -234,7 +234,7 @@ bool GCNNSAReassign::runOnMachineFunction(MachineFunction &MF) {
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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MaxNumVGPRs = ST->getMaxNumVGPRs(MF);
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MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(MFI->getOccupancy()), MaxNumVGPRs);
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CSRegs = TRI->getCalleeSavedRegs(&MF);
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CSRegs = MRI->getCalleeSavedRegs();
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using Candidate = std::pair<const MachineInstr*, bool>;
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SmallVector<Candidate, 32> Candidates;
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@ -740,7 +740,7 @@ bool GCNRegBankReassign::runOnMachineFunction(MachineFunction &MF) {
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MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(Occupancy), MaxNumVGPRs);
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MaxNumSGPRs = std::min(ST->getMaxNumSGPRs(Occupancy, true), MaxNumSGPRs);
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CSRegs = TRI->getCalleeSavedRegs(&MF);
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CSRegs = MRI->getCalleeSavedRegs();
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RegsUsed.resize(AMDGPU::VGPR_32RegClass.getNumRegs() +
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TRI->getEncodingValue(AMDGPU::SGPR_NULL) / 2 + 1);
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@ -527,15 +527,13 @@ static unsigned findScratchNonCalleeSaveRegister(MachineFunction &MF,
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LivePhysRegs &LiveRegs,
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const TargetRegisterClass &RC) {
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const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
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const SIRegisterInfo &TRI = *Subtarget.getRegisterInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Mark callee saved registers as used so we will not choose them.
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const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
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const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
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for (unsigned i = 0; CSRegs[i]; ++i)
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LiveRegs.addReg(CSRegs[i]);
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (unsigned Reg : RC) {
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if (LiveRegs.available(MRI, Reg))
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return Reg;
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@ -250,7 +250,7 @@ bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
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int NumLanes = Size / 4;
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const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
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const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
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// Make sure to handle the case where a wide SGPR spill may span between two
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// VGPRs.
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