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AMDGPU: Check MRI for callee saved regs instead of TRI

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This should the same, but MRI does allow dynamically changing the CSR
set, although currently not used.

llvm-svn: 364425
This commit is contained in:
Matt Arsenault 2019-06-26 13:39:29 +00:00
parent 2f54ed60d2
commit 752bbb8561
4 changed files with 5 additions and 7 deletions
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2
lib/Target/AMDGPU/GCNNSAReassign.cpp
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@ -234,7 +234,7 @@ bool GCNNSAReassign::runOnMachineFunction(MachineFunction &MF) {
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
MaxNumVGPRs = ST->getMaxNumVGPRs(MF); MaxNumVGPRs = ST->getMaxNumVGPRs(MF);
MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(MFI->getOccupancy()), MaxNumVGPRs); MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(MFI->getOccupancy()), MaxNumVGPRs);
CSRegs = TRI->getCalleeSavedRegs(&MF); CSRegs = MRI->getCalleeSavedRegs();
using Candidate = std::pair<const MachineInstr*, bool>; using Candidate = std::pair<const MachineInstr*, bool>;
SmallVector<Candidate, 32> Candidates; SmallVector<Candidate, 32> Candidates;

2
lib/Target/AMDGPU/GCNRegBankReassign.cpp
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@ -740,7 +740,7 @@ bool GCNRegBankReassign::runOnMachineFunction(MachineFunction &MF) {
MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(Occupancy), MaxNumVGPRs); MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(Occupancy), MaxNumVGPRs);
MaxNumSGPRs = std::min(ST->getMaxNumSGPRs(Occupancy, true), MaxNumSGPRs); MaxNumSGPRs = std::min(ST->getMaxNumSGPRs(Occupancy, true), MaxNumSGPRs);
CSRegs = TRI->getCalleeSavedRegs(&MF); CSRegs = MRI->getCalleeSavedRegs();
RegsUsed.resize(AMDGPU::VGPR_32RegClass.getNumRegs() + RegsUsed.resize(AMDGPU::VGPR_32RegClass.getNumRegs() +
TRI->getEncodingValue(AMDGPU::SGPR_NULL) / 2 + 1); TRI->getEncodingValue(AMDGPU::SGPR_NULL) / 2 + 1);

6
lib/Target/AMDGPU/SIFrameLowering.cpp
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@ -527,15 +527,13 @@ static unsigned findScratchNonCalleeSaveRegister(MachineFunction &MF,
LivePhysRegs &LiveRegs, LivePhysRegs &LiveRegs,
const TargetRegisterClass &RC) { const TargetRegisterClass &RC) {
const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
const SIRegisterInfo &TRI = *Subtarget.getRegisterInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
// Mark callee saved registers as used so we will not choose them. // Mark callee saved registers as used so we will not choose them.
const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF); const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
for (unsigned i = 0; CSRegs[i]; ++i) for (unsigned i = 0; CSRegs[i]; ++i)
LiveRegs.addReg(CSRegs[i]); LiveRegs.addReg(CSRegs[i]);
MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned Reg : RC) { for (unsigned Reg : RC) {
if (LiveRegs.available(MRI, Reg)) if (LiveRegs.available(MRI, Reg))
return Reg; return Reg;

2
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
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@ -250,7 +250,7 @@ bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
int NumLanes = Size / 4; int NumLanes = Size / 4;
const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
// Make sure to handle the case where a wide SGPR spill may span between two // Make sure to handle the case where a wide SGPR spill may span between two
// VGPRs. // VGPRs.