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[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs

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Summary:
This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency.

Apparently we were inconsistent about whether the store has latency or not thus the test changes.

I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5.

Reviewers: RKSimon, andreadb

Reviewed By: andreadb

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45351

llvm-svn: 329416
This commit is contained in:
Craig Topper 2018-04-06 16:16:48 +00:00
parent 7eb4e0e958
commit 75554e0d19
8 changed files with 454 additions and 676 deletions
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27
lib/Target/X86/X86InstrArithmetic.td
View File

@ -394,7 +394,7 @@ def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
} // Constraints = "$src1 = $dst", SchedRW
// Read-modify-write negate.
let SchedRW = [WriteALULd, WriteRMW] in {
let SchedRW = [WriteALURMW] in {
def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
"neg{b}\t$dst",
[(store (ineg (loadi8 addr:$dst)), addr:$dst),
@ -434,7 +434,7 @@ def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
}
} // Constraints = "$src1 = $dst", SchedRW
let SchedRW = [WriteALULd, WriteRMW] in {
let SchedRW = [WriteALURMW] in {
def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
"not{b}\t$dst",
[(store (not (loadi8 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
@ -485,7 +485,7 @@ def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
} // CodeSize = 1, hasSideEffects = 0
} // Constraints = "$src1 = $dst", SchedRW
let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
let CodeSize = 2, SchedRW = [WriteALURMW] in {
let Predicates = [UseIncDec] in {
def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
[(store (add (loadi8 addr:$dst), 1), addr:$dst),
@ -536,7 +536,7 @@ def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
} // Constraints = "$src1 = $dst", SchedRW
let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
let CodeSize = 2, SchedRW = [WriteALURMW] in {
let Predicates = [UseIncDec] in {
def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
[(store (add (loadi8 addr:$dst), -1), addr:$dst),
@ -835,7 +835,7 @@ class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDNode opnode>
: BinOpMR<opcode, mnemonic, typeinfo,
[(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
(implicit EFLAGS)]>, Sched<[WriteALULd, WriteRMW]>;
(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
// BinOpMR_RMW_FF - Instructions like "adc [mem], reg".
class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
@ -844,7 +844,7 @@ class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
[(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
addr:$dst),
(implicit EFLAGS)], IIC_BIN_CARRY_MEM>,
Sched<[WriteALULd, WriteRMW]>;
Sched<[WriteALURMW]>;
// BinOpMR_F - Instructions like "cmp [mem], reg".
class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
@ -852,7 +852,8 @@ class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
: BinOpMR<opcode, mnemonic, typeinfo,
[(set EFLAGS, (opnode (typeinfo.LoadNode addr:$dst),
typeinfo.RegClass:$src))]>,
Sched<[WriteALULd, ReadAfterLd]>;
Sched<[WriteALULd, ReadDefault, ReadDefault, ReadDefault,
ReadDefault, ReadDefault, ReadAfterLd]>;
// BinOpMI - Instructions like "add [mem], imm".
class BinOpMI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
@ -870,7 +871,7 @@ class BinOpMI_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
: BinOpMI<opcode, mnemonic, typeinfo, f,
[(store (opnode (typeinfo.VT (load addr:$dst)),
typeinfo.ImmOperator:$src), addr:$dst),
(implicit EFLAGS)]>, Sched<[WriteALULd, WriteRMW]>;
(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
// BinOpMI_RMW_FF - Instructions like "adc [mem], imm".
class BinOpMI_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDNode opnode, Format f>
@ -878,7 +879,7 @@ class BinOpMI_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
[(store (opnode (typeinfo.VT (load addr:$dst)),
typeinfo.ImmOperator:$src, EFLAGS), addr:$dst),
(implicit EFLAGS)], IIC_BIN_CARRY_MEM>,
Sched<[WriteALULd, WriteRMW]>;
Sched<[WriteALURMW]>;
// BinOpMI_F - Instructions like "cmp [mem], imm".
class BinOpMI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
@ -886,7 +887,7 @@ class BinOpMI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
: BinOpMI<opcode, mnemonic, typeinfo, f,
[(set EFLAGS, (opnode (typeinfo.LoadNode addr:$dst),
typeinfo.ImmOperator:$src))]>,
Sched<[WriteALULd, ReadAfterLd]>;
Sched<[WriteALULd]>;
// BinOpMI8 - Instructions like "add [mem], imm8".
class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
@ -904,7 +905,7 @@ class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
: BinOpMI8<mnemonic, typeinfo, f,
[(store (opnode (load addr:$dst),
typeinfo.Imm8Operator:$src), addr:$dst),
(implicit EFLAGS)]>, Sched<[WriteALULd, WriteRMW]>;
(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
// BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8".
class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
@ -913,7 +914,7 @@ class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
[(store (opnode (load addr:$dst),
typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),
(implicit EFLAGS)], IIC_BIN_CARRY_MEM>,
Sched<[WriteALULd, WriteRMW]>;
Sched<[WriteALURMW]>;
// BinOpMI8_F - Instructions like "cmp [mem], imm8".
class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
@ -921,7 +922,7 @@ class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
: BinOpMI8<mnemonic, typeinfo, f,
[(set EFLAGS, (opnode (typeinfo.LoadNode addr:$dst),
typeinfo.Imm8Operator:$src))]>,
Sched<[WriteALULd, ReadAfterLd]>;
Sched<[WriteALULd]>;
// BinOpAI - Instructions like "add %eax, %eax, imm", that imp-def EFLAGS.
class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,

66
lib/Target/X86/X86SchedBroadwell.td
View File

@ -605,33 +605,10 @@ def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup9], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
"CLC",
def: InstRW<[BWWriteResGroup9], (instregex "CLC",
"CMC",
"CMP(8|16|32|64)ri",
"CMP(8|16|32|64)rr",
"CMP(8|16|32|64)i",
"DEC(8|16|32|64)r",
"INC(8|16|32|64)r",
"LAHF",
"MOV(8|16|32|64)rr",
"MOV(8|16|32|64)ri",
"MOVSX(16|32|64)rr16",
"MOVSX(16|32|64)rr32",
"MOVSX(16|32|64)rr8",
"MOVZX(16|32|64)rr16",
"MOVZX(16|32|64)rr8",
"NEG(8|16|32|64)r",
"NOOP",
"NOT(8|16|32|64)r",
"OR(8|16|32|64)ri",
"OR(8|16|32|64)rr",
"OR(8|16|32|64)i",
"SAHF",
"SGDT64m",
"SIDT64m",
@ -639,17 +616,8 @@ def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
"SMSW16m",
"STC",
"STRm",
"SUB(8|16|32|64)ri",
"SUB(8|16|32|64)rr",
"SUB(8|16|32|64)i",
"SYSCALL",
"TEST(8|16|32|64)rr",
"TEST(8|16|32|64)i",
"TEST(8|16|32|64)ri",
"XCHG(16|32|64)rr",
"XOR(8|16|32|64)ri",
"XOR(8|16|32|64)rr",
"XOR(8|16|32|64)i")>;
"XCHG(16|32|64)rr")>;
def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
let Latency = 1;
@ -1553,17 +1521,7 @@ def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
"AND(8|16|32|64)rm",
"CMP(8|16|32|64)mi",
"CMP(8|16|32|64)mr",
"CMP(8|16|32|64)rm",
"OR(8|16|32|64)rm",
"POP(16|32|64)rmr",
"SUB(8|16|32|64)rm",
"TEST(8|16|32|64)mr",
"TEST(8|16|32|64)mi",
"XOR(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
let Latency = 6;
@ -1600,22 +1558,8 @@ def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
"ADD(8|16|32|64)mr",
"AND(8|16|32|64)mi",
"AND(8|16|32|64)mr",
"DEC(8|16|32|64)m",
"INC(8|16|32|64)m",
"NEG(8|16|32|64)m",
"NOT(8|16|32|64)m",
"OR(8|16|32|64)mi",
"OR(8|16|32|64)mr",
"POP(16|32|64)rmm",
"PUSH(16|32|64)rmm",
"SUB(8|16|32|64)mi",
"SUB(8|16|32|64)mr",
"XOR(8|16|32|64)mi",
"XOR(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
"PUSH(16|32|64)rmm")>;
def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
let Latency = 6;

66
lib/Target/X86/X86SchedHaswell.td
View File

@ -954,33 +954,10 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
"CLC",
def: InstRW<[HWWriteResGroup10], (instregex "CLC",
"CMC",
"CMP(8|16|32|64)ri",
"CMP(8|16|32|64)rr",
"CMP(8|16|32|64)i",
"DEC(8|16|32|64)r",
"INC(8|16|32|64)r",
"LAHF",
"MOV(8|16|32|64)rr",
"MOV(8|16|32|64)ri",
"MOVSX(16|32|64)rr16",
"MOVSX(16|32|64)rr32",
"MOVSX(16|32|64)rr8",
"MOVZX(16|32|64)rr16",
"MOVZX(16|32|64)rr8",
"NEG(8|16|32|64)r",
"NOOP",
"NOT(8|16|32|64)r",
"OR(8|16|32|64)ri",
"OR(8|16|32|64)rr",
"OR(8|16|32|64)i",
"SAHF",
"SGDT64m",
"SIDT64m",
@ -988,17 +965,8 @@ def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"SMSW16m",
"STC",
"STRm",
"SUB(8|16|32|64)ri",
"SUB(8|16|32|64)rr",
"SUB(8|16|32|64)i",
"SYSCALL",
"TEST(8|16|32|64)rr",
"TEST(8|16|32|64)i",
"TEST(8|16|32|64)ri",
"XCHG(16|32|64)rr",
"XOR(8|16|32|64)ri",
"XOR(8|16|32|64)rr",
"XOR(8|16|32|64)i")>;
"XCHG(16|32|64)rr")>;
def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 6;
@ -1409,17 +1377,7 @@ def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[HWWriteResGroup18], (instregex "ADD(8|16|32|64)rm",
"AND(8|16|32|64)rm",
"CMP(8|16|32|64)mi",
"CMP(8|16|32|64)mr",
"CMP(8|16|32|64)rm",
"OR(8|16|32|64)rm",
"POP(16|32|64)rmr",
"SUB(8|16|32|64)rm",
"TEST(8|16|32|64)mr",
"TEST(8|16|32|64)mi",
"XOR(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
let Latency = 2;
@ -1501,22 +1459,8 @@ def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[HWWriteResGroup26], (instregex "ADD(8|16|32|64)mi",
"ADD(8|16|32|64)mr",
"AND(8|16|32|64)mi",
"AND(8|16|32|64)mr",
"DEC(8|16|32|64)m",
"INC(8|16|32|64)m",
"NEG(8|16|32|64)m",
"NOT(8|16|32|64)m",
"OR(8|16|32|64)mi",
"OR(8|16|32|64)mr",
"POP(16|32|64)rmm",
"PUSH(16|32|64)rmm",
"SUB(8|16|32|64)mi",
"SUB(8|16|32|64)mr",
"XOR(8|16|32|64)mi",
"XOR(8|16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",
"PUSH(16|32|64)rmm")>;
def HWWriteResGroup27 : SchedWriteRes<[HWPort5]> {
let Latency = 2;

66
lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -609,33 +609,10 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
"CLC",
def: InstRW<[SKLWriteResGroup10], (instregex "CLC",
"CMC",
"CMP(8|16|32|64)ri",
"CMP(8|16|32|64)rr",
"CMP(8|16|32|64)i",
"DEC(8|16|32|64)r",
"INC(8|16|32|64)r",
"LAHF",
"MOV(8|16|32|64)rr",
"MOV(8|16|32|64)ri",
"MOVSX(16|32|64)rr16",
"MOVSX(16|32|64)rr32",
"MOVSX(16|32|64)rr8",
"MOVZX(16|32|64)rr16",
"MOVZX(16|32|64)rr8",
"NEG(8|16|32|64)r",
"NOOP",
"NOT(8|16|32|64)r",
"OR(8|16|32|64)ri",
"OR(8|16|32|64)rr",
"OR(8|16|32|64)i",
"SAHF",
"SGDT64m",
"SIDT64m",
@ -643,17 +620,8 @@ def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"SMSW16m",
"STC",
"STRm",
"SUB(8|16|32|64)ri",
"SUB(8|16|32|64)rr",
"SUB(8|16|32|64)i",
"SYSCALL",
"TEST(8|16|32|64)rr",
"TEST(8|16|32|64)i",
"TEST(8|16|32|64)ri",
"XCHG(16|32|64)rr",
"XOR(8|16|32|64)ri",
"XOR(8|16|32|64)rr",
"XOR(8|16|32|64)i")>;
"XCHG(16|32|64)rr")>;
def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
let Latency = 1;
@ -1480,17 +1448,7 @@ def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[SKLWriteResGroup76], (instregex "ADD(8|16|32|64)rm",
"AND(8|16|32|64)rm",
"CMP(8|16|32|64)mi",
"CMP(8|16|32|64)mr",
"CMP(8|16|32|64)rm",
"OR(8|16|32|64)rm",
"POP(16|32|64)rmr",
"SUB(8|16|32|64)rm",
"TEST(8|16|32|64)mr",
"TEST(8|16|32|64)mi",
"XOR(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
def SKLWriteResGroup77 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 6;
@ -1551,22 +1509,8 @@ def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort015
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKLWriteResGroup83], (instregex "ADD(8|16|32|64)mi",
"ADD(8|16|32|64)mr",
"AND(8|16|32|64)mi",
"AND(8|16|32|64)mr",
"DEC(8|16|32|64)m",
"INC(8|16|32|64)m",
"NEG(8|16|32|64)m",
"NOT(8|16|32|64)m",
"OR(8|16|32|64)mi",
"OR(8|16|32|64)mr",
"POP(16|32|64)rmm",
"PUSH(16|32|64)rmm",
"SUB(8|16|32|64)mi",
"SUB(8|16|32|64)mr",
"XOR(8|16|32|64)mi",
"XOR(8|16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
"PUSH(16|32|64)rmm")>;
def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 6;

66
lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -1269,33 +1269,10 @@ def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
"CLC",
def: InstRW<[SKXWriteResGroup10], (instregex "CLC",
"CMC",
"CMP(8|16|32|64)ri",
"CMP(8|16|32|64)rr",
"CMP(8|16|32|64)i",
"DEC(8|16|32|64)r",
"INC(8|16|32|64)r",
"LAHF",
"MOV(8|16|32|64)rr",
"MOV(8|16|32|64)ri",
"MOVSX(16|32|64)rr16",
"MOVSX(16|32|64)rr32",
"MOVSX(16|32|64)rr8",
"MOVZX(16|32|64)rr16",
"MOVZX(16|32|64)rr8",
"NEG(8|16|32|64)r",
"NOOP",
"NOT(8|16|32|64)r",
"OR(8|16|32|64)ri",
"OR(8|16|32|64)rr",
"OR(8|16|32|64)i",
"SAHF",
"SGDT64m",
"SIDT64m",
@ -1303,17 +1280,8 @@ def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"SMSW16m",
"STC",
"STRm",
"SUB(8|16|32|64)ri",
"SUB(8|16|32|64)rr",
"SUB(8|16|32|64)i",
"SYSCALL",
"TEST(8|16|32|64)rr",
"TEST(8|16|32|64)i",
"TEST(8|16|32|64)ri",
"XCHG(16|32|64)rr",
"XOR(8|16|32|64)ri",
"XOR(8|16|32|64)rr",
"XOR(8|16|32|64)i")>;
"XCHG(16|32|64)rr")>;
def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
let Latency = 1;
@ -3117,17 +3085,7 @@ def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[SKXWriteResGroup81], (instregex "ADD(8|16|32|64)rm",
"AND(8|16|32|64)rm",
"CMP(8|16|32|64)mi",
"CMP(8|16|32|64)mr",
"CMP(8|16|32|64)rm",
"OR(8|16|32|64)rm",
"POP(16|32|64)rmr",
"SUB(8|16|32|64)rm",
"TEST(8|16|32|64)mr",
"TEST(8|16|32|64)mi",
"XOR(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 6;
@ -3193,22 +3151,8 @@ def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort015
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKXWriteResGroup87], (instregex "ADD(8|16|32|64)mi",
"ADD(8|16|32|64)mr",
"AND(8|16|32|64)mi",
"AND(8|16|32|64)mr",
"DEC(8|16|32|64)m",
"INC(8|16|32|64)m",
"NEG(8|16|32|64)m",
"NOT(8|16|32|64)m",
"OR(8|16|32|64)mi",
"OR(8|16|32|64)mr",
"POP(16|32|64)rmm",
"PUSH(16|32|64)rmm",
"SUB(8|16|32|64)mi",
"SUB(8|16|32|64)mr",
"XOR(8|16|32|64)mi",
"XOR(8|16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
"PUSH(16|32|64)rmm")>;
def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
let Latency = 6;

1
lib/Target/X86/X86Schedule.td
View File

@ -41,6 +41,7 @@ multiclass X86SchedWritePair {
// Arithmetic.
defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>;
defm WriteIMul : X86SchedWritePair; // Integer multiplication.
def WriteIMulH : SchedWrite; // Integer multiplication, high part.
defm WriteIDiv : X86SchedWritePair; // Integer division.

40
test/CodeGen/X86/schedule-x86_32.ll
View File

@ -800,7 +800,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: decw %ax # sched: [1:0.50]
; SLM-NEXT: decw (%ecx) # sched: [4:2.00]
; SLM-NEXT: decw (%ecx) # sched: [5:2.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
@ -830,7 +830,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: decw %ax # sched: [1:0.25]
; BROADWELL-NEXT: decw (%ecx) # sched: [6:1.00]
; BROADWELL-NEXT: decw (%ecx) # sched: [7:1.00]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
@ -840,7 +840,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: decw %ax # sched: [1:0.25]
; SKYLAKE-NEXT: decw (%ecx) # sched: [6:1.00]
; SKYLAKE-NEXT: decw (%ecx) # sched: [7:1.00]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
@ -850,7 +850,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: decw %ax # sched: [1:0.25]
; SKX-NEXT: decw (%ecx) # sched: [6:1.00]
; SKX-NEXT: decw (%ecx) # sched: [7:1.00]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
@ -860,7 +860,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: decw %ax # sched: [1:0.50]
; BTVER2-NEXT: decw (%ecx) # sched: [4:1.00]
; BTVER2-NEXT: decw (%ecx) # sched: [5:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
@ -903,7 +903,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: decl %eax # sched: [1:0.50]
; SLM-NEXT: decl (%ecx) # sched: [4:2.00]
; SLM-NEXT: decl (%ecx) # sched: [5:2.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
@ -933,7 +933,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: decl %eax # sched: [1:0.25]
; BROADWELL-NEXT: decl (%ecx) # sched: [6:1.00]
; BROADWELL-NEXT: decl (%ecx) # sched: [7:1.00]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
@ -943,7 +943,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: decl %eax # sched: [1:0.25]
; SKYLAKE-NEXT: decl (%ecx) # sched: [6:1.00]
; SKYLAKE-NEXT: decl (%ecx) # sched: [7:1.00]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
@ -953,7 +953,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: decl %eax # sched: [1:0.25]
; SKX-NEXT: decl (%ecx) # sched: [6:1.00]
; SKX-NEXT: decl (%ecx) # sched: [7:1.00]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
@ -963,7 +963,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: decl %eax # sched: [1:0.50]
; BTVER2-NEXT: decl (%ecx) # sched: [4:1.00]
; BTVER2-NEXT: decl (%ecx) # sched: [5:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
@ -1007,7 +1007,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: incw %ax # sched: [1:0.50]
; SLM-NEXT: incw (%ecx) # sched: [4:2.00]
; SLM-NEXT: incw (%ecx) # sched: [5:2.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
@ -1037,7 +1037,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: incw %ax # sched: [1:0.25]
; BROADWELL-NEXT: incw (%ecx) # sched: [6:1.00]
; BROADWELL-NEXT: incw (%ecx) # sched: [7:1.00]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
@ -1047,7 +1047,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: incw %ax # sched: [1:0.25]
; SKYLAKE-NEXT: incw (%ecx) # sched: [6:1.00]
; SKYLAKE-NEXT: incw (%ecx) # sched: [7:1.00]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
@ -1057,7 +1057,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: incw %ax # sched: [1:0.25]
; SKX-NEXT: incw (%ecx) # sched: [6:1.00]
; SKX-NEXT: incw (%ecx) # sched: [7:1.00]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
@ -1067,7 +1067,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: incw %ax # sched: [1:0.50]
; BTVER2-NEXT: incw (%ecx) # sched: [4:1.00]
; BTVER2-NEXT: incw (%ecx) # sched: [5:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
@ -1110,7 +1110,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: incl %eax # sched: [1:0.50]
; SLM-NEXT: incl (%ecx) # sched: [4:2.00]
; SLM-NEXT: incl (%ecx) # sched: [5:2.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
@ -1140,7 +1140,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: incl %eax # sched: [1:0.25]
; BROADWELL-NEXT: incl (%ecx) # sched: [6:1.00]
; BROADWELL-NEXT: incl (%ecx) # sched: [7:1.00]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
@ -1150,7 +1150,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: incl %eax # sched: [1:0.25]
; SKYLAKE-NEXT: incl (%ecx) # sched: [6:1.00]
; SKYLAKE-NEXT: incl (%ecx) # sched: [7:1.00]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
@ -1160,7 +1160,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: incl %eax # sched: [1:0.25]
; SKX-NEXT: incl (%ecx) # sched: [6:1.00]
; SKX-NEXT: incl (%ecx) # sched: [7:1.00]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
@ -1170,7 +1170,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: incl %eax # sched: [1:0.50]
; BTVER2-NEXT: incl (%ecx) # sched: [4:1.00]
; BTVER2-NEXT: incl (%ecx) # sched: [5:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;

798
test/CodeGen/X86/schedule-x86_64.ll
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