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[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs
Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
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@ -394,7 +394,7 @@ def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
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} // Constraints = "$src1 = $dst", SchedRW
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// Read-modify-write negate.
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let SchedRW = [WriteALULd, WriteRMW] in {
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let SchedRW = [WriteALURMW] in {
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def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
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"neg{b}\t$dst",
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[(store (ineg (loadi8 addr:$dst)), addr:$dst),
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@ -434,7 +434,7 @@ def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
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}
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} // Constraints = "$src1 = $dst", SchedRW
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let SchedRW = [WriteALULd, WriteRMW] in {
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let SchedRW = [WriteALURMW] in {
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def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
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"not{b}\t$dst",
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[(store (not (loadi8 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
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@ -485,7 +485,7 @@ def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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} // CodeSize = 1, hasSideEffects = 0
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} // Constraints = "$src1 = $dst", SchedRW
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let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
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let CodeSize = 2, SchedRW = [WriteALURMW] in {
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let Predicates = [UseIncDec] in {
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def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
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[(store (add (loadi8 addr:$dst), 1), addr:$dst),
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@ -536,7 +536,7 @@ def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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} // Constraints = "$src1 = $dst", SchedRW
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let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
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let CodeSize = 2, SchedRW = [WriteALURMW] in {
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let Predicates = [UseIncDec] in {
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def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
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[(store (add (loadi8 addr:$dst), -1), addr:$dst),
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@ -835,7 +835,7 @@ class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpMR<opcode, mnemonic, typeinfo,
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[(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
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(implicit EFLAGS)]>, Sched<[WriteALULd, WriteRMW]>;
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(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
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// BinOpMR_RMW_FF - Instructions like "adc [mem], reg".
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class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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@ -844,7 +844,7 @@ class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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[(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
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addr:$dst),
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(implicit EFLAGS)], IIC_BIN_CARRY_MEM>,
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Sched<[WriteALULd, WriteRMW]>;
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Sched<[WriteALURMW]>;
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// BinOpMR_F - Instructions like "cmp [mem], reg".
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class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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@ -852,7 +852,8 @@ class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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: BinOpMR<opcode, mnemonic, typeinfo,
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[(set EFLAGS, (opnode (typeinfo.LoadNode addr:$dst),
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typeinfo.RegClass:$src))]>,
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Sched<[WriteALULd, ReadAfterLd]>;
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Sched<[WriteALULd, ReadDefault, ReadDefault, ReadDefault,
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ReadDefault, ReadDefault, ReadAfterLd]>;
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// BinOpMI - Instructions like "add [mem], imm".
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class BinOpMI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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@ -870,7 +871,7 @@ class BinOpMI_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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: BinOpMI<opcode, mnemonic, typeinfo, f,
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[(store (opnode (typeinfo.VT (load addr:$dst)),
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typeinfo.ImmOperator:$src), addr:$dst),
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(implicit EFLAGS)]>, Sched<[WriteALULd, WriteRMW]>;
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(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
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// BinOpMI_RMW_FF - Instructions like "adc [mem], imm".
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class BinOpMI_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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@ -878,7 +879,7 @@ class BinOpMI_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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[(store (opnode (typeinfo.VT (load addr:$dst)),
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typeinfo.ImmOperator:$src, EFLAGS), addr:$dst),
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(implicit EFLAGS)], IIC_BIN_CARRY_MEM>,
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Sched<[WriteALULd, WriteRMW]>;
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Sched<[WriteALURMW]>;
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// BinOpMI_F - Instructions like "cmp [mem], imm".
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class BinOpMI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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@ -886,7 +887,7 @@ class BinOpMI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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: BinOpMI<opcode, mnemonic, typeinfo, f,
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[(set EFLAGS, (opnode (typeinfo.LoadNode addr:$dst),
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typeinfo.ImmOperator:$src))]>,
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Sched<[WriteALULd, ReadAfterLd]>;
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Sched<[WriteALULd]>;
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// BinOpMI8 - Instructions like "add [mem], imm8".
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class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
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@ -904,7 +905,7 @@ class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
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: BinOpMI8<mnemonic, typeinfo, f,
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[(store (opnode (load addr:$dst),
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typeinfo.Imm8Operator:$src), addr:$dst),
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(implicit EFLAGS)]>, Sched<[WriteALULd, WriteRMW]>;
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(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
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// BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8".
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class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
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@ -913,7 +914,7 @@ class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
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[(store (opnode (load addr:$dst),
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typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),
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(implicit EFLAGS)], IIC_BIN_CARRY_MEM>,
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Sched<[WriteALULd, WriteRMW]>;
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Sched<[WriteALURMW]>;
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// BinOpMI8_F - Instructions like "cmp [mem], imm8".
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class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
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@ -921,7 +922,7 @@ class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
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: BinOpMI8<mnemonic, typeinfo, f,
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[(set EFLAGS, (opnode (typeinfo.LoadNode addr:$dst),
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typeinfo.Imm8Operator:$src))]>,
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Sched<[WriteALULd, ReadAfterLd]>;
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Sched<[WriteALULd]>;
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// BinOpAI - Instructions like "add %eax, %eax, imm", that imp-def EFLAGS.
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class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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@ -605,33 +605,10 @@ def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
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let ResourceCycles = [1];
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}
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def: InstRW<[BWWriteResGroup9], (instrs CBW, CWDE, CDQE)>;
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def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
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"ADD(8|16|32|64)rr",
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"ADD(8|16|32|64)i",
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"AND(8|16|32|64)ri",
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"AND(8|16|32|64)rr",
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"AND(8|16|32|64)i",
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"CLC",
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def: InstRW<[BWWriteResGroup9], (instregex "CLC",
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"CMC",
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"CMP(8|16|32|64)ri",
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"CMP(8|16|32|64)rr",
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"CMP(8|16|32|64)i",
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"DEC(8|16|32|64)r",
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"INC(8|16|32|64)r",
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"LAHF",
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"MOV(8|16|32|64)rr",
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"MOV(8|16|32|64)ri",
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"MOVSX(16|32|64)rr16",
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"MOVSX(16|32|64)rr32",
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"MOVSX(16|32|64)rr8",
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"MOVZX(16|32|64)rr16",
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"MOVZX(16|32|64)rr8",
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"NEG(8|16|32|64)r",
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"NOOP",
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"NOT(8|16|32|64)r",
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"OR(8|16|32|64)ri",
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"OR(8|16|32|64)rr",
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"OR(8|16|32|64)i",
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"SAHF",
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"SGDT64m",
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"SIDT64m",
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@ -639,17 +616,8 @@ def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
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"SMSW16m",
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"STC",
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"STRm",
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"SUB(8|16|32|64)ri",
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"SUB(8|16|32|64)rr",
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"SUB(8|16|32|64)i",
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"SYSCALL",
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"TEST(8|16|32|64)rr",
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"TEST(8|16|32|64)i",
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"TEST(8|16|32|64)ri",
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"XCHG(16|32|64)rr",
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"XOR(8|16|32|64)ri",
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"XOR(8|16|32|64)rr",
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"XOR(8|16|32|64)i")>;
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"XCHG(16|32|64)rr")>;
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def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
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let Latency = 1;
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@ -1553,17 +1521,7 @@ def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
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let ResourceCycles = [1,1];
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}
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def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
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def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
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"AND(8|16|32|64)rm",
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"CMP(8|16|32|64)mi",
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"CMP(8|16|32|64)mr",
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"CMP(8|16|32|64)rm",
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"OR(8|16|32|64)rm",
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"POP(16|32|64)rmr",
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"SUB(8|16|32|64)rm",
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"TEST(8|16|32|64)mr",
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"TEST(8|16|32|64)mi",
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"XOR(8|16|32|64)rm")>;
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def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
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def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
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let Latency = 6;
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@ -1600,22 +1558,8 @@ def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
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let NumMicroOps = 4;
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let ResourceCycles = [1,1,1,1];
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}
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def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
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"ADD(8|16|32|64)mr",
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"AND(8|16|32|64)mi",
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"AND(8|16|32|64)mr",
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"DEC(8|16|32|64)m",
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"INC(8|16|32|64)m",
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"NEG(8|16|32|64)m",
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"NOT(8|16|32|64)m",
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"OR(8|16|32|64)mi",
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"OR(8|16|32|64)mr",
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"POP(16|32|64)rmm",
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"PUSH(16|32|64)rmm",
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"SUB(8|16|32|64)mi",
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"SUB(8|16|32|64)mr",
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"XOR(8|16|32|64)mi",
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"XOR(8|16|32|64)mr")>;
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def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
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"PUSH(16|32|64)rmm")>;
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def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
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let Latency = 6;
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@ -954,33 +954,10 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
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let ResourceCycles = [1];
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}
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def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
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def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
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"ADD(8|16|32|64)rr",
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"ADD(8|16|32|64)i",
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"AND(8|16|32|64)ri",
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"AND(8|16|32|64)rr",
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"AND(8|16|32|64)i",
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"CLC",
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def: InstRW<[HWWriteResGroup10], (instregex "CLC",
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"CMC",
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"CMP(8|16|32|64)ri",
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"CMP(8|16|32|64)rr",
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"CMP(8|16|32|64)i",
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"DEC(8|16|32|64)r",
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"INC(8|16|32|64)r",
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"LAHF",
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"MOV(8|16|32|64)rr",
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"MOV(8|16|32|64)ri",
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"MOVSX(16|32|64)rr16",
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"MOVSX(16|32|64)rr32",
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"MOVSX(16|32|64)rr8",
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"MOVZX(16|32|64)rr16",
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"MOVZX(16|32|64)rr8",
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"NEG(8|16|32|64)r",
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"NOOP",
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"NOT(8|16|32|64)r",
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"OR(8|16|32|64)ri",
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"OR(8|16|32|64)rr",
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"OR(8|16|32|64)i",
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"SAHF",
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"SGDT64m",
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"SIDT64m",
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@ -988,17 +965,8 @@ def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
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"SMSW16m",
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"STC",
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"STRm",
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"SUB(8|16|32|64)ri",
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"SUB(8|16|32|64)rr",
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"SUB(8|16|32|64)i",
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"SYSCALL",
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"TEST(8|16|32|64)rr",
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"TEST(8|16|32|64)i",
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"TEST(8|16|32|64)ri",
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"XCHG(16|32|64)rr",
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"XOR(8|16|32|64)ri",
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"XOR(8|16|32|64)rr",
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"XOR(8|16|32|64)i")>;
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"XCHG(16|32|64)rr")>;
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def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
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let Latency = 6;
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@ -1409,17 +1377,7 @@ def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
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let ResourceCycles = [1,1];
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}
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def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
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def: InstRW<[HWWriteResGroup18], (instregex "ADD(8|16|32|64)rm",
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"AND(8|16|32|64)rm",
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"CMP(8|16|32|64)mi",
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"CMP(8|16|32|64)mr",
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"CMP(8|16|32|64)rm",
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"OR(8|16|32|64)rm",
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"POP(16|32|64)rmr",
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"SUB(8|16|32|64)rm",
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"TEST(8|16|32|64)mr",
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"TEST(8|16|32|64)mi",
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"XOR(8|16|32|64)rm")>;
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def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
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def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
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let Latency = 2;
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@ -1501,22 +1459,8 @@ def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
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let NumMicroOps = 4;
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let ResourceCycles = [1,1,1,1];
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}
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def: InstRW<[HWWriteResGroup26], (instregex "ADD(8|16|32|64)mi",
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"ADD(8|16|32|64)mr",
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"AND(8|16|32|64)mi",
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"AND(8|16|32|64)mr",
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"DEC(8|16|32|64)m",
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"INC(8|16|32|64)m",
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"NEG(8|16|32|64)m",
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"NOT(8|16|32|64)m",
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"OR(8|16|32|64)mi",
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"OR(8|16|32|64)mr",
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"POP(16|32|64)rmm",
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"PUSH(16|32|64)rmm",
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"SUB(8|16|32|64)mi",
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"SUB(8|16|32|64)mr",
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"XOR(8|16|32|64)mi",
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"XOR(8|16|32|64)mr")>;
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def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",
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"PUSH(16|32|64)rmm")>;
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def HWWriteResGroup27 : SchedWriteRes<[HWPort5]> {
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let Latency = 2;
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@ -609,33 +609,10 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
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let ResourceCycles = [1];
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}
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def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
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def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
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"ADD(8|16|32|64)rr",
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"ADD(8|16|32|64)i",
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"AND(8|16|32|64)ri",
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"AND(8|16|32|64)rr",
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"AND(8|16|32|64)i",
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"CLC",
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def: InstRW<[SKLWriteResGroup10], (instregex "CLC",
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"CMC",
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"CMP(8|16|32|64)ri",
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"CMP(8|16|32|64)rr",
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"CMP(8|16|32|64)i",
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"DEC(8|16|32|64)r",
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"INC(8|16|32|64)r",
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"LAHF",
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"MOV(8|16|32|64)rr",
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"MOV(8|16|32|64)ri",
|
||||
"MOVSX(16|32|64)rr16",
|
||||
"MOVSX(16|32|64)rr32",
|
||||
"MOVSX(16|32|64)rr8",
|
||||
"MOVZX(16|32|64)rr16",
|
||||
"MOVZX(16|32|64)rr8",
|
||||
"NEG(8|16|32|64)r",
|
||||
"NOOP",
|
||||
"NOT(8|16|32|64)r",
|
||||
"OR(8|16|32|64)ri",
|
||||
"OR(8|16|32|64)rr",
|
||||
"OR(8|16|32|64)i",
|
||||
"SAHF",
|
||||
"SGDT64m",
|
||||
"SIDT64m",
|
||||
@ -643,17 +620,8 @@ def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
|
||||
"SMSW16m",
|
||||
"STC",
|
||||
"STRm",
|
||||
"SUB(8|16|32|64)ri",
|
||||
"SUB(8|16|32|64)rr",
|
||||
"SUB(8|16|32|64)i",
|
||||
"SYSCALL",
|
||||
"TEST(8|16|32|64)rr",
|
||||
"TEST(8|16|32|64)i",
|
||||
"TEST(8|16|32|64)ri",
|
||||
"XCHG(16|32|64)rr",
|
||||
"XOR(8|16|32|64)ri",
|
||||
"XOR(8|16|32|64)rr",
|
||||
"XOR(8|16|32|64)i")>;
|
||||
"XCHG(16|32|64)rr")>;
|
||||
|
||||
def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
|
||||
let Latency = 1;
|
||||
@ -1480,17 +1448,7 @@ def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
|
||||
let ResourceCycles = [1,1];
|
||||
}
|
||||
def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
|
||||
def: InstRW<[SKLWriteResGroup76], (instregex "ADD(8|16|32|64)rm",
|
||||
"AND(8|16|32|64)rm",
|
||||
"CMP(8|16|32|64)mi",
|
||||
"CMP(8|16|32|64)mr",
|
||||
"CMP(8|16|32|64)rm",
|
||||
"OR(8|16|32|64)rm",
|
||||
"POP(16|32|64)rmr",
|
||||
"SUB(8|16|32|64)rm",
|
||||
"TEST(8|16|32|64)mr",
|
||||
"TEST(8|16|32|64)mi",
|
||||
"XOR(8|16|32|64)rm")>;
|
||||
def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
|
||||
|
||||
def SKLWriteResGroup77 : SchedWriteRes<[SKLPort5,SKLPort01]> {
|
||||
let Latency = 6;
|
||||
@ -1551,22 +1509,8 @@ def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort015
|
||||
let NumMicroOps = 4;
|
||||
let ResourceCycles = [1,1,1,1];
|
||||
}
|
||||
def: InstRW<[SKLWriteResGroup83], (instregex "ADD(8|16|32|64)mi",
|
||||
"ADD(8|16|32|64)mr",
|
||||
"AND(8|16|32|64)mi",
|
||||
"AND(8|16|32|64)mr",
|
||||
"DEC(8|16|32|64)m",
|
||||
"INC(8|16|32|64)m",
|
||||
"NEG(8|16|32|64)m",
|
||||
"NOT(8|16|32|64)m",
|
||||
"OR(8|16|32|64)mi",
|
||||
"OR(8|16|32|64)mr",
|
||||
"POP(16|32|64)rmm",
|
||||
"PUSH(16|32|64)rmm",
|
||||
"SUB(8|16|32|64)mi",
|
||||
"SUB(8|16|32|64)mr",
|
||||
"XOR(8|16|32|64)mi",
|
||||
"XOR(8|16|32|64)mr")>;
|
||||
def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
|
||||
"PUSH(16|32|64)rmm")>;
|
||||
|
||||
def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
|
||||
let Latency = 6;
|
||||
|
@ -1269,33 +1269,10 @@ def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
|
||||
let ResourceCycles = [1];
|
||||
}
|
||||
def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
|
||||
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
|
||||
"ADD(8|16|32|64)rr",
|
||||
"ADD(8|16|32|64)i",
|
||||
"AND(8|16|32|64)ri",
|
||||
"AND(8|16|32|64)rr",
|
||||
"AND(8|16|32|64)i",
|
||||
"CLC",
|
||||
def: InstRW<[SKXWriteResGroup10], (instregex "CLC",
|
||||
"CMC",
|
||||
"CMP(8|16|32|64)ri",
|
||||
"CMP(8|16|32|64)rr",
|
||||
"CMP(8|16|32|64)i",
|
||||
"DEC(8|16|32|64)r",
|
||||
"INC(8|16|32|64)r",
|
||||
"LAHF",
|
||||
"MOV(8|16|32|64)rr",
|
||||
"MOV(8|16|32|64)ri",
|
||||
"MOVSX(16|32|64)rr16",
|
||||
"MOVSX(16|32|64)rr32",
|
||||
"MOVSX(16|32|64)rr8",
|
||||
"MOVZX(16|32|64)rr16",
|
||||
"MOVZX(16|32|64)rr8",
|
||||
"NEG(8|16|32|64)r",
|
||||
"NOOP",
|
||||
"NOT(8|16|32|64)r",
|
||||
"OR(8|16|32|64)ri",
|
||||
"OR(8|16|32|64)rr",
|
||||
"OR(8|16|32|64)i",
|
||||
"SAHF",
|
||||
"SGDT64m",
|
||||
"SIDT64m",
|
||||
@ -1303,17 +1280,8 @@ def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
|
||||
"SMSW16m",
|
||||
"STC",
|
||||
"STRm",
|
||||
"SUB(8|16|32|64)ri",
|
||||
"SUB(8|16|32|64)rr",
|
||||
"SUB(8|16|32|64)i",
|
||||
"SYSCALL",
|
||||
"TEST(8|16|32|64)rr",
|
||||
"TEST(8|16|32|64)i",
|
||||
"TEST(8|16|32|64)ri",
|
||||
"XCHG(16|32|64)rr",
|
||||
"XOR(8|16|32|64)ri",
|
||||
"XOR(8|16|32|64)rr",
|
||||
"XOR(8|16|32|64)i")>;
|
||||
"XCHG(16|32|64)rr")>;
|
||||
|
||||
def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
|
||||
let Latency = 1;
|
||||
@ -3117,17 +3085,7 @@ def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
|
||||
let ResourceCycles = [1,1];
|
||||
}
|
||||
def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
|
||||
def: InstRW<[SKXWriteResGroup81], (instregex "ADD(8|16|32|64)rm",
|
||||
"AND(8|16|32|64)rm",
|
||||
"CMP(8|16|32|64)mi",
|
||||
"CMP(8|16|32|64)mr",
|
||||
"CMP(8|16|32|64)rm",
|
||||
"OR(8|16|32|64)rm",
|
||||
"POP(16|32|64)rmr",
|
||||
"SUB(8|16|32|64)rm",
|
||||
"TEST(8|16|32|64)mr",
|
||||
"TEST(8|16|32|64)mi",
|
||||
"XOR(8|16|32|64)rm")>;
|
||||
def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
|
||||
|
||||
def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
|
||||
let Latency = 6;
|
||||
@ -3193,22 +3151,8 @@ def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort015
|
||||
let NumMicroOps = 4;
|
||||
let ResourceCycles = [1,1,1,1];
|
||||
}
|
||||
def: InstRW<[SKXWriteResGroup87], (instregex "ADD(8|16|32|64)mi",
|
||||
"ADD(8|16|32|64)mr",
|
||||
"AND(8|16|32|64)mi",
|
||||
"AND(8|16|32|64)mr",
|
||||
"DEC(8|16|32|64)m",
|
||||
"INC(8|16|32|64)m",
|
||||
"NEG(8|16|32|64)m",
|
||||
"NOT(8|16|32|64)m",
|
||||
"OR(8|16|32|64)mi",
|
||||
"OR(8|16|32|64)mr",
|
||||
"POP(16|32|64)rmm",
|
||||
"PUSH(16|32|64)rmm",
|
||||
"SUB(8|16|32|64)mi",
|
||||
"SUB(8|16|32|64)mr",
|
||||
"XOR(8|16|32|64)mi",
|
||||
"XOR(8|16|32|64)mr")>;
|
||||
def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
|
||||
"PUSH(16|32|64)rmm")>;
|
||||
|
||||
def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
|
||||
let Latency = 6;
|
||||
|
@ -41,6 +41,7 @@ multiclass X86SchedWritePair {
|
||||
|
||||
// Arithmetic.
|
||||
defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
|
||||
def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>;
|
||||
defm WriteIMul : X86SchedWritePair; // Integer multiplication.
|
||||
def WriteIMulH : SchedWrite; // Integer multiplication, high part.
|
||||
defm WriteIDiv : X86SchedWritePair; // Integer division.
|
||||
|
@ -800,7 +800,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
|
||||
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
|
||||
; SLM-NEXT: #APP
|
||||
; SLM-NEXT: decw %ax # sched: [1:0.50]
|
||||
; SLM-NEXT: decw (%ecx) # sched: [4:2.00]
|
||||
; SLM-NEXT: decw (%ecx) # sched: [5:2.00]
|
||||
; SLM-NEXT: #NO_APP
|
||||
; SLM-NEXT: retl # sched: [4:1.00]
|
||||
;
|
||||
@ -830,7 +830,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
|
||||
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; BROADWELL-NEXT: #APP
|
||||
; BROADWELL-NEXT: decw %ax # sched: [1:0.25]
|
||||
; BROADWELL-NEXT: decw (%ecx) # sched: [6:1.00]
|
||||
; BROADWELL-NEXT: decw (%ecx) # sched: [7:1.00]
|
||||
; BROADWELL-NEXT: #NO_APP
|
||||
; BROADWELL-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -840,7 +840,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
|
||||
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; SKYLAKE-NEXT: #APP
|
||||
; SKYLAKE-NEXT: decw %ax # sched: [1:0.25]
|
||||
; SKYLAKE-NEXT: decw (%ecx) # sched: [6:1.00]
|
||||
; SKYLAKE-NEXT: decw (%ecx) # sched: [7:1.00]
|
||||
; SKYLAKE-NEXT: #NO_APP
|
||||
; SKYLAKE-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -850,7 +850,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
|
||||
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; SKX-NEXT: #APP
|
||||
; SKX-NEXT: decw %ax # sched: [1:0.25]
|
||||
; SKX-NEXT: decw (%ecx) # sched: [6:1.00]
|
||||
; SKX-NEXT: decw (%ecx) # sched: [7:1.00]
|
||||
; SKX-NEXT: #NO_APP
|
||||
; SKX-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -860,7 +860,7 @@ define void @test_dec16(i16 %a0, i16* %a1) optsize {
|
||||
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
|
||||
; BTVER2-NEXT: #APP
|
||||
; BTVER2-NEXT: decw %ax # sched: [1:0.50]
|
||||
; BTVER2-NEXT: decw (%ecx) # sched: [4:1.00]
|
||||
; BTVER2-NEXT: decw (%ecx) # sched: [5:1.00]
|
||||
; BTVER2-NEXT: #NO_APP
|
||||
; BTVER2-NEXT: retl # sched: [4:1.00]
|
||||
;
|
||||
@ -903,7 +903,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
|
||||
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
|
||||
; SLM-NEXT: #APP
|
||||
; SLM-NEXT: decl %eax # sched: [1:0.50]
|
||||
; SLM-NEXT: decl (%ecx) # sched: [4:2.00]
|
||||
; SLM-NEXT: decl (%ecx) # sched: [5:2.00]
|
||||
; SLM-NEXT: #NO_APP
|
||||
; SLM-NEXT: retl # sched: [4:1.00]
|
||||
;
|
||||
@ -933,7 +933,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
|
||||
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; BROADWELL-NEXT: #APP
|
||||
; BROADWELL-NEXT: decl %eax # sched: [1:0.25]
|
||||
; BROADWELL-NEXT: decl (%ecx) # sched: [6:1.00]
|
||||
; BROADWELL-NEXT: decl (%ecx) # sched: [7:1.00]
|
||||
; BROADWELL-NEXT: #NO_APP
|
||||
; BROADWELL-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -943,7 +943,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
|
||||
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; SKYLAKE-NEXT: #APP
|
||||
; SKYLAKE-NEXT: decl %eax # sched: [1:0.25]
|
||||
; SKYLAKE-NEXT: decl (%ecx) # sched: [6:1.00]
|
||||
; SKYLAKE-NEXT: decl (%ecx) # sched: [7:1.00]
|
||||
; SKYLAKE-NEXT: #NO_APP
|
||||
; SKYLAKE-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -953,7 +953,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
|
||||
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; SKX-NEXT: #APP
|
||||
; SKX-NEXT: decl %eax # sched: [1:0.25]
|
||||
; SKX-NEXT: decl (%ecx) # sched: [6:1.00]
|
||||
; SKX-NEXT: decl (%ecx) # sched: [7:1.00]
|
||||
; SKX-NEXT: #NO_APP
|
||||
; SKX-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -963,7 +963,7 @@ define void @test_dec32(i32 %a0, i32* %a1) optsize {
|
||||
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
|
||||
; BTVER2-NEXT: #APP
|
||||
; BTVER2-NEXT: decl %eax # sched: [1:0.50]
|
||||
; BTVER2-NEXT: decl (%ecx) # sched: [4:1.00]
|
||||
; BTVER2-NEXT: decl (%ecx) # sched: [5:1.00]
|
||||
; BTVER2-NEXT: #NO_APP
|
||||
; BTVER2-NEXT: retl # sched: [4:1.00]
|
||||
;
|
||||
@ -1007,7 +1007,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
|
||||
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
|
||||
; SLM-NEXT: #APP
|
||||
; SLM-NEXT: incw %ax # sched: [1:0.50]
|
||||
; SLM-NEXT: incw (%ecx) # sched: [4:2.00]
|
||||
; SLM-NEXT: incw (%ecx) # sched: [5:2.00]
|
||||
; SLM-NEXT: #NO_APP
|
||||
; SLM-NEXT: retl # sched: [4:1.00]
|
||||
;
|
||||
@ -1037,7 +1037,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
|
||||
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; BROADWELL-NEXT: #APP
|
||||
; BROADWELL-NEXT: incw %ax # sched: [1:0.25]
|
||||
; BROADWELL-NEXT: incw (%ecx) # sched: [6:1.00]
|
||||
; BROADWELL-NEXT: incw (%ecx) # sched: [7:1.00]
|
||||
; BROADWELL-NEXT: #NO_APP
|
||||
; BROADWELL-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -1047,7 +1047,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
|
||||
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; SKYLAKE-NEXT: #APP
|
||||
; SKYLAKE-NEXT: incw %ax # sched: [1:0.25]
|
||||
; SKYLAKE-NEXT: incw (%ecx) # sched: [6:1.00]
|
||||
; SKYLAKE-NEXT: incw (%ecx) # sched: [7:1.00]
|
||||
; SKYLAKE-NEXT: #NO_APP
|
||||
; SKYLAKE-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -1057,7 +1057,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
|
||||
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; SKX-NEXT: #APP
|
||||
; SKX-NEXT: incw %ax # sched: [1:0.25]
|
||||
; SKX-NEXT: incw (%ecx) # sched: [6:1.00]
|
||||
; SKX-NEXT: incw (%ecx) # sched: [7:1.00]
|
||||
; SKX-NEXT: #NO_APP
|
||||
; SKX-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -1067,7 +1067,7 @@ define void @test_inc16(i16 %a0, i16* %a1) optsize {
|
||||
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
|
||||
; BTVER2-NEXT: #APP
|
||||
; BTVER2-NEXT: incw %ax # sched: [1:0.50]
|
||||
; BTVER2-NEXT: incw (%ecx) # sched: [4:1.00]
|
||||
; BTVER2-NEXT: incw (%ecx) # sched: [5:1.00]
|
||||
; BTVER2-NEXT: #NO_APP
|
||||
; BTVER2-NEXT: retl # sched: [4:1.00]
|
||||
;
|
||||
@ -1110,7 +1110,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
|
||||
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
|
||||
; SLM-NEXT: #APP
|
||||
; SLM-NEXT: incl %eax # sched: [1:0.50]
|
||||
; SLM-NEXT: incl (%ecx) # sched: [4:2.00]
|
||||
; SLM-NEXT: incl (%ecx) # sched: [5:2.00]
|
||||
; SLM-NEXT: #NO_APP
|
||||
; SLM-NEXT: retl # sched: [4:1.00]
|
||||
;
|
||||
@ -1140,7 +1140,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
|
||||
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; BROADWELL-NEXT: #APP
|
||||
; BROADWELL-NEXT: incl %eax # sched: [1:0.25]
|
||||
; BROADWELL-NEXT: incl (%ecx) # sched: [6:1.00]
|
||||
; BROADWELL-NEXT: incl (%ecx) # sched: [7:1.00]
|
||||
; BROADWELL-NEXT: #NO_APP
|
||||
; BROADWELL-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -1150,7 +1150,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
|
||||
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; SKYLAKE-NEXT: #APP
|
||||
; SKYLAKE-NEXT: incl %eax # sched: [1:0.25]
|
||||
; SKYLAKE-NEXT: incl (%ecx) # sched: [6:1.00]
|
||||
; SKYLAKE-NEXT: incl (%ecx) # sched: [7:1.00]
|
||||
; SKYLAKE-NEXT: #NO_APP
|
||||
; SKYLAKE-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -1160,7 +1160,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
|
||||
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
|
||||
; SKX-NEXT: #APP
|
||||
; SKX-NEXT: incl %eax # sched: [1:0.25]
|
||||
; SKX-NEXT: incl (%ecx) # sched: [6:1.00]
|
||||
; SKX-NEXT: incl (%ecx) # sched: [7:1.00]
|
||||
; SKX-NEXT: #NO_APP
|
||||
; SKX-NEXT: retl # sched: [6:0.50]
|
||||
;
|
||||
@ -1170,7 +1170,7 @@ define void @test_inc32(i32 %a0, i32* %a1) optsize {
|
||||
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
|
||||
; BTVER2-NEXT: #APP
|
||||
; BTVER2-NEXT: incl %eax # sched: [1:0.50]
|
||||
; BTVER2-NEXT: incl (%ecx) # sched: [4:1.00]
|
||||
; BTVER2-NEXT: incl (%ecx) # sched: [5:1.00]
|
||||
; BTVER2-NEXT: #NO_APP
|
||||
; BTVER2-NEXT: retl # sched: [4:1.00]
|
||||
;
|
||||
|
File diff suppressed because it is too large
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Reference in New Issue
Block a user