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[WebAssembly][NFC] Standardize SIMD multiclass format

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Summary:
This CL changes the ExtractLane ISEL multiclass to more closely mirror
the structure of the splat and replace_lane multiclasses.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50794

llvm-svn: 339801
This commit is contained in:
Thomas Lively 2018-08-15 18:15:18 +00:00
parent 69450b777d
commit 7557bac2f3
1 changed files with 30 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
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@ -18,14 +18,15 @@ foreach SIZE = [2, 4, 8, 16, 32] in
def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
// lane extraction
multiclass ExtractLane<ValueType vec_t, ImmLeaf imm_t,
WebAssemblyRegClass reg_t, string name, bits<32> simdop,
SDNode extract = vector_extract> {
defm "" : SIMD_I<(outs reg_t:$dst), (ins V128:$vec, I32:$idx),
multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t,
WebAssemblyRegClass reg_t, bits<32> simdop,
string suffix = "", SDNode extract = vector_extract> {
defm EXTRACT_LANE_#vec_t#suffix :
SIMD_I<(outs reg_t:$dst), (ins V128:$vec, I32:$idx),
(outs), (ins I32:$idx),
[(set reg_t:$dst,
(extract (vec_t V128:$vec), (i32 imm_t:$idx)))],
name#"\t$dst, $vec, $idx", name#"\t$idx", simdop>;
[(set reg_t:$dst, (extract (vec_t V128:$vec), (i32 imm_t:$idx)))],
vec#".extract_lane"#suffix#"\t$dst, $vec, $idx",
vec#".extract_lane"#suffix#"\t$idx", simdop>;
}
multiclass ExtractPat<ValueType lane_t, int mask> {
def _s : PatFrag<(ops node:$vec, node:$idx),
@ -48,41 +49,34 @@ multiclass ExtractPat<ValueType lane_t, int mask> {
defm extract_i8x16 : ExtractPat<i8, 0xff>;
defm extract_i16x8 : ExtractPat<i16, 0xffff>;
multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
defm _I8x16 : ExtractLane<v16i8, LaneIdx16, I32, "i8x16.extract_lane"#sign,
baseInst, !cast<PatFrag>("extract_i8x16"#sign)>;
defm _I16x8 : ExtractLane<v8i16, LaneIdx8, I32, "i16x8.extract_lane"#sign,
!add(baseInst, 2),
defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign,
!cast<PatFrag>("extract_i8x16"#sign)>;
defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 2), sign,
!cast<PatFrag>("extract_i16x8"#sign)>;
}
let Defs = [ARGUMENTS] in {
defm EXTRACT_LANE_S : ExtractLaneExtended<"_s", 9>;
defm EXTRACT_LANE_U : ExtractLaneExtended<"_u", 10>;
defm EXTRACT_LANE_I32x4 :
ExtractLane<v4i32, LaneIdx4, I32, "i32x4.extract_lane", 13>;
defm EXTRACT_LANE_I64x2 :
ExtractLane<v2i64, LaneIdx2, I64, "i64x2.extract_lane", 14>;
defm EXTRACT_LANE_F32x4 :
ExtractLane<v4f32, LaneIdx4, F32, "f32x4.extract_lane", 15>;
defm EXTRACT_LANE_F64x2 :
ExtractLane<v2f64, LaneIdx2, F64, "f64x2.extract_lane", 16>;
defm "" : ExtractLaneExtended<"_s", 9>;
defm "" : ExtractLaneExtended<"_u", 10>;
defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 14>;
defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 15>;
defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 16>;
} // Defs = [ARGUMENTS]
// follow convention of making implicit expansions unsigned
def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
(EXTRACT_LANE_U_I8x16 V128:$vec, (i32 LaneIdx16:$idx))>;
(EXTRACT_LANE_v16i8_u V128:$vec, (i32 LaneIdx16:$idx))>;
def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
(EXTRACT_LANE_U_I16x8 V128:$vec, (i32 LaneIdx8:$idx))>;
(EXTRACT_LANE_v8i16_u V128:$vec, (i32 LaneIdx8:$idx))>;
// lane replacement
multiclass ReplaceLane<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
ValueType lane_t, ImmLeaf imm_t, bits<32> simdop> {
defm REPLACE_LANE_#vec_t : SIMD_I<(outs V128:$dst),
(ins V128:$vec, I32:$idx, reg_t:$x),
defm REPLACE_LANE_#vec_t :
SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$idx, reg_t:$x),
(outs), (ins I32:$idx),
[(set V128:$dst, (vector_insert
(vec_t V128:$vec),
(lane_t reg_t:$x),
(i32 imm_t:$idx)))],
(vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))],
vec#".replace_lane\t$dst, $vec, $idx, $x",
vec#".replace_lane\t$idx", simdop>;
}
@ -107,11 +101,11 @@ def splat16 : PatFrag<(ops node:$x), (build_vector
node:$x, node:$x, node:$x, node:$x,
node:$x, node:$x, node:$x, node:$x,
node:$x, node:$x, node:$x, node:$x)>;
multiclass Splat<ValueType vec_t, string name, WebAssemblyRegClass reg_t,
multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
PatFrag splat_pat, bits<32> simdop> {
defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
[(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
name#".splat\t$dst, $x", name#".splat", simdop>;
vec#".splat\t$dst, $x", vec#".splat", simdop>;
}
let Defs = [ARGUMENTS] in {
defm "" : Splat<v16i8, "i8x16", I32, splat16, 3>;