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Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)

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llvm-svn: 198945
This commit is contained in:
Artyom Skrobov 2014-01-10 16:42:55 +00:00
parent f544263238
commit 759f6384e9
4 changed files with 18 additions and 15 deletions
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22
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -630,15 +630,19 @@ void ARMAsmPrinter::emitAttributes() {
ATS.emitAttribute(ARMBuildAttrs::CPU_arch, ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
getArchForCPU(CPUString, Subtarget)); getArchForCPU(CPUString, Subtarget));
if (Subtarget->isAClass()) { // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, // profile is not applicable (e.g. pre v7, or cross-profile code)".
ARMBuildAttrs::ApplicationProfile); if (Subtarget->hasV7Ops()) {
} else if (Subtarget->isRClass()) { if (Subtarget->isAClass()) {
ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
ARMBuildAttrs::RealTimeProfile); ARMBuildAttrs::ApplicationProfile);
} else if (Subtarget->isMClass()){ } else if (Subtarget->isRClass()) {
ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
ARMBuildAttrs::MicroControllerProfile); ARMBuildAttrs::RealTimeProfile);
} else if (Subtarget->isMClass()) {
ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
ARMBuildAttrs::MicroControllerProfile);
}
} }
ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ? ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?

1
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
View File

@ -692,7 +692,6 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
break; break;
case ARM::ARMV6M: case ARM::ARMV6M:
setAttributeItem(CPU_arch_profile, MicroControllerProfile, false);
setAttributeItem(THUMB_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false);
break; break;

4
test/CodeGen/ARM/build-attributes.ll
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@ -43,7 +43,7 @@
; V6-NOT: .eabi_attribute 68 ; V6-NOT: .eabi_attribute 68
; V6M: .eabi_attribute 6, 12 ; V6M: .eabi_attribute 6, 12
; V6M: .eabi_attribute 7, 77 ; V6M-NOT: .eabi_attribute 7
; V6M: .eabi_attribute 8, 0 ; V6M: .eabi_attribute 8, 0
; V6M: .eabi_attribute 9, 1 ; V6M: .eabi_attribute 9, 1
; V6M: .eabi_attribute 24, 1 ; V6M: .eabi_attribute 24, 1
@ -333,7 +333,7 @@
; CORTEX-M0: .cpu cortex-m0 ; CORTEX-M0: .cpu cortex-m0
; CORTEX-M0: .eabi_attribute 6, 12 ; CORTEX-M0: .eabi_attribute 6, 12
; CORTEX-M0: .eabi_attribute 7, 77 ; CORTEX-M0-NOT: .eabi_attribute 7
; CORTEX-M0: .eabi_attribute 8, 0 ; CORTEX-M0: .eabi_attribute 8, 0
; CORTEX-M0: .eabi_attribute 9, 1 ; CORTEX-M0: .eabi_attribute 9, 1
; CORTEX-M0: .eabi_attribute 24, 1 ; CORTEX-M0: .eabi_attribute 24, 1

6
test/MC/ARM/directive-arch-armv6-m.s
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@ -19,12 +19,12 @@
@ CHECK-OBJ: ] @ CHECK-OBJ: ]
@ CHECK-OBJ: Address: 0x0 @ CHECK-OBJ: Address: 0x0
@ CHECK-OBJ: Offset: 0x34 @ CHECK-OBJ: Offset: 0x34
@ CHECK-OBJ: Size: 27 @ CHECK-OBJ: Size: 25
@ CHECK-OBJ: Link: 0 @ CHECK-OBJ: Link: 0
@ CHECK-OBJ: Info: 0 @ CHECK-OBJ: Info: 0
@ CHECK-OBJ: AddressAlignment: 1 @ CHECK-OBJ: AddressAlignment: 1
@ CHECK-OBJ: EntrySize: 0 @ CHECK-OBJ: EntrySize: 0
@ CHECK-OBJ: SectionData ( @ CHECK-OBJ: SectionData (
@ CHECK-OBJ: 0000: 411A0000 00616561 62690001 10000000 |A....aeabi......| @ CHECK-OBJ: 0000: 41180000 00616561 62690001 0E000000 |A....aeabi......|
@ CHECK-OBJ: 0010: 05362D4D 00060B07 4D0901 |.6-M....M..| @ CHECK-OBJ: 0010: 05362D4D 00060B09 01 |.6-M.....|
@ CHECK-OBJ: ) @ CHECK-OBJ: )