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A simplification for checking whether the signs of the operands and sum differ. Thanks, Duncan.

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llvm-svn: 60043
This commit is contained in:
Bill Wendling 2008-11-25 19:40:17 +00:00
parent c11d7e324f
commit 75a3f4dc3d
1 changed files with 12 additions and 13 deletions
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25
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -4187,21 +4187,20 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
SDValue Zero = DAG.getConstant(0, LHS.getValueType());
SDValue LHSPos = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
SDValue RHSPos = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
SDValue And1 = DAG.getNode(ISD::AND, OType, LHSPos, RHSPos);
// LHSSign -> LHS >= 0
// RHSSign -> RHS >= 0
// SumSign -> Sum >= 0
//
// Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
//
SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
SDValue SignsEq = DAG.getSetCC(OType, LHSSign, RHSSign, ISD::SETEQ);
And1 = DAG.getNode(ISD::AND, OType, And1,
DAG.getSetCC(OType, Sum, Zero, ISD::SETLT));
SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE);
SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE);
SDValue LHSNeg = DAG.getSetCC(OType, LHS, Zero, ISD::SETLT);
SDValue RHSNeg = DAG.getSetCC(OType, RHS, Zero, ISD::SETLT);
SDValue And2 = DAG.getNode(ISD::AND, OType, LHSNeg, RHSNeg);
And2 = DAG.getNode(ISD::AND, OType, And2,
DAG.getSetCC(OType, Sum, Zero, ISD::SETGE));
SDValue Cmp = DAG.getNode(ISD::OR, OType, And1, And2);
SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsEq, SumSignNE);
MVT ValueVTs[] = { LHS.getValueType(), OType };
SDValue Ops[] = { Sum, Cmp };