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[X86] Add vcvtsd2sil/vcvtsd2siq etc. InstAliases to the EVEX-encoded instructions.
This matches their VEX equivalents. llvm-svn: 321912
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@ -6456,7 +6456,7 @@ def : Pat<(f64 (uint_to_fp GR64:$src)),
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multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT,
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X86VectorVTInfo DstVT, SDNode OpNode,
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OpndItins itins, string asm> {
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OpndItins itins, string asm, string aliasStr> {
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let Predicates = [HasAVX512] in {
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def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
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@ -6473,33 +6473,41 @@ multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT,
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(SrcVT.VT SrcVT.ScalarIntMemCPat:$src),
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(i32 FROUND_CURRENT)))], itins.rm>,
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EVEX, VEX_LIG, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}",
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(!cast<Instruction>(NAME # "rr_Int") DstVT.RC:$dst, SrcVT.RC:$src), 0>;
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def : InstAlias<"v" # asm # aliasStr # "\t{$rc, $src, $dst|$dst, $src, $rc}",
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(!cast<Instruction>(NAME # "rrb_Int") DstVT.RC:$dst, SrcVT.RC:$src, AVX512RC:$rc), 0>;
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def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}",
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(!cast<Instruction>(NAME # "rm_Int") DstVT.RC:$dst,
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SrcVT.IntScalarMemOp:$src), 0>;
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} // Predicates = [HasAVX512]
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}
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// Convert float/double to signed/unsigned int 32/64
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defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info,
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X86cvts2si, SSE_CVT_SS2SI_32, "cvtss2si">,
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X86cvts2si, SSE_CVT_SS2SI_32, "cvtss2si", "{l}">,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info,
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X86cvts2si, SSE_CVT_SS2SI_64, "cvtss2si">,
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X86cvts2si, SSE_CVT_SS2SI_64, "cvtss2si", "{q}">,
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XS, VEX_W, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info,
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X86cvts2usi, SSE_CVT_SS2SI_32, "cvtss2usi">,
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X86cvts2usi, SSE_CVT_SS2SI_32, "cvtss2usi", "{l}">,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info,
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X86cvts2usi, SSE_CVT_SS2SI_64, "cvtss2usi">,
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X86cvts2usi, SSE_CVT_SS2SI_64, "cvtss2usi", "{q}">,
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XS, VEX_W, EVEX_CD8<32, CD8VT1>;
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defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info,
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X86cvts2si, SSE_CVT_SD2SI, "cvtsd2si">,
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X86cvts2si, SSE_CVT_SD2SI, "cvtsd2si", "{l}">,
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XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info,
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X86cvts2si, SSE_CVT_SD2SI, "cvtsd2si">,
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X86cvts2si, SSE_CVT_SD2SI, "cvtsd2si", "{q}">,
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XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, f64x_info, i32x_info,
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X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi">,
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X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi", "{l}">,
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XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info,
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X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi">,
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X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi", "{q}">,
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XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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// The SSE version of these instructions are disabled for AVX512.
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@ -6590,7 +6598,7 @@ let Predicates = [HasAVX512] in {
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def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
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(!cast<Instruction>(NAME # "rr") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
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def : InstAlias<asm # aliasStr # "\t\t{{sae}, $src, $dst|$dst, $src, {sae}}",
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def : InstAlias<asm # aliasStr # "\t{{sae}, $src, $dst|$dst, $src, {sae}}",
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(!cast<Instruction>(NAME # "rrb") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
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def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
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(!cast<Instruction>(NAME # "rm") _DstRC.RC:$dst,
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@ -19685,3 +19685,67 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
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// CHECK: vmovq %xmm31, %rax
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// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x7e,0xf8]
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vmovd %xmm31, %rax
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// CHECK: vcvtsd2si %xmm16, %eax
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// CHECK: encoding: [0x62,0xb1,0x7f,0x08,0x2d,0xc0]
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vcvtsd2sil %xmm16, %eax
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// CHECK: vcvtsd2si (%rax), %ebx
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// CHECK: encoding: [0x62,0xf1,0x7f,0x08,0x2d,0x18]
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vcvtsd2sil (%rax), %ebx
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// CHECK: vcvtss2si %xmm16, %eax
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// CHECK: encoding: [0x62,0xb1,0x7e,0x08,0x2d,0xc0]
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vcvtss2sil %xmm16, %eax
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// CHECK: vcvtss2si (%rax), %ebx
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// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x2d,0x18]
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vcvtss2sil (%rax), %ebx
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// CHECK: vcvtsd2si %xmm16, %rax
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// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x2d,0xc0]
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vcvtsd2siq %xmm16, %rax
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// CHECK: vcvtsd2si (%rax), %rbx
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// CHECK: encoding: [0x62,0xf1,0xff,0x08,0x2d,0x18]
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vcvtsd2siq (%rax), %rbx
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// CHECK: vcvtss2si %xmm16, %rax
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// CHECK: encoding: [0x62,0xb1,0xfe,0x08,0x2d,0xc0]
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vcvtss2siq %xmm16, %rax
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// CHECK: vcvtss2si (%rax), %rbx
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// CHECK: encoding: [0x62,0xf1,0xfe,0x08,0x2d,0x18]
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vcvtss2siq (%rax), %rbx
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// CHECK: vcvtsd2usi %xmm16, %eax
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// CHECK: encoding: [0x62,0xb1,0x7f,0x08,0x79,0xc0]
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vcvtsd2usil %xmm16, %eax
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// CHECK: vcvtsd2usi (%rax), %ebx
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// CHECK: encoding: [0x62,0xf1,0x7f,0x08,0x79,0x18]
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vcvtsd2usil (%rax), %ebx
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// CHECK: vcvtss2usi %xmm16, %eax
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// CHECK: encoding: [0x62,0xb1,0x7e,0x08,0x79,0xc0]
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vcvtss2usil %xmm16, %eax
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// CHECK: vcvtss2usi (%rax), %ebx
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// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x79,0x18]
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vcvtss2usil (%rax), %ebx
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// CHECK: vcvtsd2usi %xmm16, %rax
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// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x79,0xc0]
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vcvtsd2usiq %xmm16, %rax
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// CHECK: vcvtsd2usi (%rax), %rbx
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// CHECK: encoding: [0x62,0xf1,0xff,0x08,0x79,0x18]
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vcvtsd2usiq (%rax), %rbx
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// CHECK: vcvtss2usi %xmm16, %rax
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// CHECK: encoding: [0x62,0xb1,0xfe,0x08,0x79,0xc0]
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vcvtss2usiq %xmm16, %rax
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// CHECK: vcvtss2usi (%rax), %rbx
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// CHECK: encoding: [0x62,0xf1,0xfe,0x08,0x79,0x18]
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vcvtss2usiq (%rax), %rbx
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