RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 05:01:59 +01:00
Code Issues Projects Releases Wiki Activity

Replace subregister uses when processing tied operands

Browse Source 
This was for some reason skipping operands that are subregisters
instead of keeping the same subregister index.

v_movreld_b32 expects src0 to be the subregister of the tied
super register use/def.

e.g.

v_movreld_b32 v0, v9, <imp-def, tied3> v[0:3], <imp-use, tied2> v[0:3]

was being replaced with

v[4:7] = copy v[0:3]
v_movreld_b32 v0, v9, <imp-def, tied3> v[4:7], <imp-use, tied2> v[4:7],

which really writes to v[0:3]

llvm-svn: 279804
This commit is contained in:
Matt Arsenault 2016-08-26 06:31:32 +00:00
parent 98992196d9
commit 7621e40810
3 changed files with 36 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -1567,14 +1567,14 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
if (!IsEarlyClobber) {
// Replace other (un-tied) uses of regB with LastCopiedReg.
for (MachineOperand &MO : MI->operands()) {
if (MO.isReg() && MO.getReg() == RegB && MO.getSubReg() == SubRegB &&
if (MO.isReg() && MO.getReg() == RegB &&
MO.isUse()) {
if (MO.isKill()) {
MO.setIsKill(false);
RemovedKillFlag = true;
}
MO.setReg(LastCopiedReg);
MO.setSubReg(0);
MO.setSubReg(MO.getSubReg());
}
}
}

19
test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll Normal file
View File

@ -0,0 +1,19 @@
; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
; FIXME: Merge into indirect-addressing-si.ll
; Make sure that TwoAddressInstructions keeps src0 as subregister sub0
; of the tied implicit use and def of the super register.
; CHECK-LABEL: {{^}}insert_wo_offset:
; CHECK: s_load_dword [[IN:s[0-9]+]]
; CHECK: s_mov_b32 m0, [[IN]]
; CHECK: v_movreld_b32_e32 v[[ELT0:[0-9]+]]
; CHECK-NEXT: buffer_store_dwordx4 v{{\[}}[[ELT0]]:
define void @insert_wo_offset(<4 x float> addrspace(1)* %out, i32 %in) {
entry:
%ins = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in
store <4 x float> %ins, <4 x float> addrspace(1)* %out
ret void
}

25
test/CodeGen/AMDGPU/indirect-addressing-si.ll
View File

@ -125,27 +125,32 @@ entry:
}
; CHECK-LABEL: {{^}}insert_w_offset:
; CHECK: s_load_dword [[IN:s[0-9]+]]
; CHECK: s_mov_b32 m0, [[IN]]
; CHECK: v_movreld_b32_e32
define void @insert_w_offset(float addrspace(1)* %out, i32 %in) {
; CHECK-DAG: s_load_dword [[IN:s[0-9]+]]
; CHECK-DAG: s_mov_b32 m0, [[IN]]
; CHECK-DAG: v_mov_b32_e32 v[[ELT0:[0-9]+]], 1.0
; CHECK-DAG: v_mov_b32_e32 v[[ELT1:[0-9]+]], 2.0
; CHECK-DAG: v_mov_b32_e32 v[[ELT2:[0-9]+]], 0x40400000
; CHECK-DAG: v_mov_b32_e32 v[[ELT3:[0-9]+]], 4.0
; CHECK-DAG: v_mov_b32_e32 v[[INS:[0-9]+]], 0x40a00000
; CHECK: v_movreld_b32_e32 v[[ELT1]], v[[INS]]
; CHECK: buffer_store_dwordx4 v{{\[}}[[ELT0]]:[[ELT3]]{{\]}}
define void @insert_w_offset(<4 x float> addrspace(1)* %out, i32 %in) {
entry:
%0 = add i32 %in, 1
%1 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %0
%2 = extractelement <4 x float> %1, i32 2
store float %2, float addrspace(1)* %out
store <4 x float> %1, <4 x float> addrspace(1)* %out
ret void
}
; CHECK-LABEL: {{^}}insert_wo_offset:
; CHECK: s_load_dword [[IN:s[0-9]+]]
; CHECK: s_mov_b32 m0, [[IN]]
; CHECK: v_movreld_b32_e32
define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) {
; CHECK: v_movreld_b32_e32 v[[ELT0:[0-9]+]]
; CHECK: buffer_store_dwordx4 v{{\[}}[[ELT0]]:
define void @insert_wo_offset(<4 x float> addrspace(1)* %out, i32 %in) {
entry:
%0 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in
%1 = extractelement <4 x float> %0, i32 2
store float %1, float addrspace(1)* %out
store <4 x float> %0, <4 x float> addrspace(1)* %out
ret void
}