diff --git a/lib/Target/PowerPC/PowerPC.h b/lib/Target/PowerPC/PowerPC.h new file mode 100644 index 00000000000..8ce3dbd83fe --- /dev/null +++ b/lib/Target/PowerPC/PowerPC.h @@ -0,0 +1,27 @@ +//===-- PowerPC.h - Top-level interface for PowerPC representation -*- C++ -*-// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the entry points for global functions defined in the LLVM +// PowerPC back-end. +// +//===----------------------------------------------------------------------===// + +#ifndef TARGET_POWERPC_H +#define TARGET_POWERPC_H + +// Defines symbolic names for PowerPC registers. This defines a mapping from +// register name to register number. +// +#include "PowerPCGenRegisterNames.inc" + +// Defines symbolic names for the PowerPC instructions. +// +#include "PowerPCGenInstrNames.inc" + +#endif diff --git a/lib/Target/PowerPC/PowerPCInstrs.td b/lib/Target/PowerPC/PowerPCInstrs.td new file mode 100644 index 00000000000..0536fef1e81 --- /dev/null +++ b/lib/Target/PowerPC/PowerPCInstrs.td @@ -0,0 +1,46 @@ +//===- PowerPCInstrInfo.td - Describe the PowerPC Instruction Set -*- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +class Format val> { + bits<4> Value = val; +} + +// All of the PowerPC instruction formats, plus a pseudo-instruction format: +def Pseudo : Format<0>; +def IForm : Format<1>; +def BForm : Format<2>; +def SCForm : Format<3>; +def DForm : Format<4>; +def XForm : Format<5>; +def XLForm : Format<6>; +def XFXForm : Format<7>; +def XFLForm : Format<8>; +def XOForm : Format<9>; +def AForm : Format<10>; +def MForm : Format<11>; + +class PPCInst opcd, Format f> : Instruction { + let Namespace = "PowerPC"; + + let Name = nm; + bits<6> Opcode = opcd; + Format Form = f; + bits<4> FormBits = Form.Value; +} + +// Pseudo-instructions: +def PHI : PPCInst<"PHI", 0, Pseudo>; // PHI node... +def NOP : PPCInst<"NOP", 0, Pseudo>; // No-op +def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>; +def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>; + + diff --git a/lib/Target/PowerPC/PowerPCReg.td b/lib/Target/PowerPC/PowerPCReg.td new file mode 100644 index 00000000000..8f856217d44 --- /dev/null +++ b/lib/Target/PowerPC/PowerPCReg.td @@ -0,0 +1,82 @@ +//===- PowerPCReg.td - Describe the PowerPC Register File -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +class PPCReg : Register { + let Namespace = "PowerPC"; +} + +// We identify all our registers with a 5-bit ID, for consistency's sake. + +// GPR - One of the 32 32-bit general-purpose registers +class GPR num> : PPCReg { + field bits<5> Num = num; +} + +// SPR - One of the 32-bit special-purpose registers +class SPR num> : PPCReg { + field bits<5> Num = num; +} + +// FPR - One of the 32 64-bit floating-point registers +class FPR num> : PPCReg { + field bits<5> Num = num; +} + +// CR - One of the 8 4-bit condition registers +class CR num> : PPCReg { + field bits<5> Num = num; +} + +// General-purpose registers +def R0 : GPR< 0>; def R1 : GPR< 1>; def R2 : GPR< 2>; def R3 : GPR< 3>; +def R4 : GPR< 4>; def R5 : GPR< 5>; def R6 : GPR< 6>; def R7 : GPR< 7>; +def R8 : GPR< 8>; def R9 : GPR< 9>; def R10 : GPR<10>; def R11 : GPR<11>; +def R12 : GPR<12>; def R13 : GPR<13>; def R14 : GPR<14>; def R15 : GPR<15>; +def R16 : GPR<16>; def R17 : GPR<17>; def R18 : GPR<18>; def R19 : GPR<19>; +def R20 : GPR<20>; def R21 : GPR<21>; def R22 : GPR<22>; def R23 : GPR<23>; +def R24 : GPR<24>; def R25 : GPR<25>; def R26 : GPR<26>; def R27 : GPR<27>; +def R28 : GPR<28>; def R29 : GPR<29>; def R30 : GPR<30>; def R31 : GPR<31>; + +// Floating-point registers +def F0 : FPR< 0>; def F1 : FPR< 1>; def F2 : FPR< 2>; def F3 : FPR< 3>; +def F4 : FPR< 4>; def F5 : FPR< 5>; def F6 : FPR< 6>; def F7 : FPR< 7>; +def F8 : FPR< 8>; def F9 : FPR< 9>; def F10 : FPR<10>; def F11 : FPR<11>; +def F12 : FPR<12>; def F13 : FPR<13>; def F14 : FPR<14>; def F15 : FPR<15>; +def F16 : FPR<16>; def F17 : FPR<17>; def F18 : FPR<18>; def F19 : FPR<19>; +def F20 : FPR<20>; def F21 : FPR<21>; def F22 : FPR<22>; def F23 : FPR<23>; +def F24 : FPR<24>; def F25 : FPR<25>; def F26 : FPR<26>; def F27 : FPR<27>; +def F28 : FPR<28>; def F29 : FPR<29>; def F30 : FPR<30>; def F31 : FPR<31>; + +// Condition registers +def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>; +def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>; + +// Floating-point status and control register +def FPSCR : SPR<0>; +// fiXed-point Exception Register? :-) +def XER : SPR<1>; +// Link register +def LR : SPR<2>; +// Count register +def CTR : SPR<3>; +// These are the "time base" registers which are read-only in user mode. +def TBL : SPR<4>; +def TBU : SPR<5>; + +/// Register classes: one for floats and another for non-floats. +def GPRC : RegisterClass; +def FPRC : RegisterClass; + diff --git a/lib/Target/PowerPC/PowerPCTargetMachine.cpp b/lib/Target/PowerPC/PowerPCTargetMachine.cpp new file mode 100644 index 00000000000..11b5a799b12 --- /dev/null +++ b/lib/Target/PowerPC/PowerPCTargetMachine.cpp @@ -0,0 +1,53 @@ +//===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "PowerPCTargetMachine.h" +#include "llvm/Module.h" +#include "llvm/PassManager.h" +#include "llvm/Target/TargetMachineImpls.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/Passes.h" + +namespace llvm { + +// allocatePowerPCTargetMachine - Allocate and return a subclass of +// TargetMachine that implements the PowerPC backend. +// +TargetMachine *allocatePowerPCTargetMachine(const Module &M, + IntrinsicLowering *IL) { + return new PowerPCTargetMachine(M, IL); +} + +/// PowerPCTargetMachine ctor - Create an ILP32 architecture model +/// +PowerPCTargetMachine::PowerPCTargetMachine(const Module &M, + IntrinsicLowering *IL) + : TargetMachine("PowerPC", IL, true, 4, 4, 4, 4, 4), + FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 4) { +} + +// addPassesToEmitAssembly - We currently use all of the same passes as the JIT +// does to emit statically compiled machine code. +bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM, + std::ostream &Out) { + return true; +} + +/// addPassesToJITCompile - Add passes to the specified pass manager to +/// implement a fast dynamic compiler for this target. Return true if this is +/// not supported for this target. +/// +bool PowerPCTargetMachine::addPassesToJITCompile(FunctionPassManager &PM) { + return true; +} + +} // end namespace llvm