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Add preliminary v2f32 support for SPU. Like with v2i32, we just
duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. llvm-svn: 110037
This commit is contained in:
Kalle Raiskila
parent
e957c57ebb
commit
766fd434df
@ -28,7 +28,7 @@ def RetCC_SPU : CallingConv<[
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CCIfType<[i128], CCAssignToReg<[R3]>>,
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CCIfType<[f32, f64], CCAssignToReg<[R3]>>,
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[R3]>>,
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CCIfType<[v2i32], CCAssignToReg<[R3]>>
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CCIfType<[v2i32, v2f32], CCAssignToReg<[R3]>>
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]>;
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@ -37,7 +37,7 @@ def RetCC_SPU : CallingConv<[
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//===----------------------------------------------------------------------===//
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def CCC_SPU : CallingConv<[
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CCIfType<[i8, i16, i32, i64, i128, f32, f64,
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v16i8, v8i16, v4i32, v4f32, v2i64, v2f64, v2i32],
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v16i8, v8i16, v4i32, v4f32, v2i64, v2f64, v2i32, v2f32],
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CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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@ -428,6 +428,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// "Odd size" vector classes that we're willing to support:
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addRegisterClass(MVT::v2i32, SPU::VECREGRegisterClass);
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addRegisterClass(MVT::v2f32, SPU::VECREGRegisterClass);
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for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
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@ -1068,6 +1069,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain,
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case MVT::v8i16:
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case MVT::v16i8:
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case MVT::v2i32:
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case MVT::v2f32:
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ArgRegClass = &SPU::VECREGRegClass;
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break;
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}
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@ -3892,6 +3892,7 @@ class FAVecInst<ValueType vectype>:
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multiclass SFPAdd
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{
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def v4f32: FAVecInst<v4f32>;
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def v2f32: FAVecInst<v2f32>;
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def f32: FAInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
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[(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
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}
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@ -3910,12 +3911,87 @@ class FSVecInst<ValueType vectype>:
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multiclass SFPSub
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{
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def v4f32: FSVecInst<v4f32>;
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def v2f32: FSVecInst<v2f32>;
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def f32: FSInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
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[(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
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}
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defm FS : SFPSub;
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class FMInst<dag OOL, dag IOL, list<dag> pattern>:
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RRForm<0b01100011010, OOL, IOL,
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"fm\t$rT, $rA, $rB", SPrecFP,
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pattern>;
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class FMVecInst<ValueType type>:
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FMInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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[(set (type VECREG:$rT),
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(fmul (type VECREG:$rA), (type VECREG:$rB)))]>;
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multiclass SFPMul
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{
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def v4f32: FMVecInst<v4f32>;
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def v2f32: FMVecInst<v2f32>;
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def f32: FMInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
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[(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
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}
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defm FM : SFPMul;
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// Floating point multiply and add
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// e.g. d = c + (a * b)
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def FMAv4f32:
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RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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"fma\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set (v4f32 VECREG:$rT),
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(fadd (v4f32 VECREG:$rC),
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(fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
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def FMAf32:
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RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
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"fma\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
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// FP multiply and subtract
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// Subtracts value in rC from product
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// res = a * b - c
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def FMSv4f32 :
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RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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"fms\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set (v4f32 VECREG:$rT),
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(fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
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(v4f32 VECREG:$rC)))]>;
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def FMSf32 :
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RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
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"fms\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set R32FP:$rT,
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(fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
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// Floating Negative Mulitply and Subtract
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// Subtracts product from value in rC
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// res = fneg(fms a b c)
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// = - (a * b - c)
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// = c - a * b
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// NOTE: subtraction order
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// fsub a b = a - b
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// fs a b = b - a?
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def FNMSf32 :
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RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
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"fnms\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
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def FNMSv4f32 :
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RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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"fnms\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set (v4f32 VECREG:$rT),
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(fsub (v4f32 VECREG:$rC),
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(fmul (v4f32 VECREG:$rA),
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(v4f32 VECREG:$rB))))]>;
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// Floating point reciprocal estimate
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class FRESTInst<dag OOL, dag IOL>:
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@ -4040,72 +4116,6 @@ def FSCRRf32 :
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// status and control register write
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// status and control register read
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//--------------------------------------
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// Floating point multiply instructions
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//--------------------------------------
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def FMv4f32:
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RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"fm\t$rT, $rA, $rB", SPrecFP,
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[(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
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(v4f32 VECREG:$rB)))]>;
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def FMf32 :
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RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
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"fm\t$rT, $rA, $rB", SPrecFP,
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[(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
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// Floating point multiply and add
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// e.g. d = c + (a * b)
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def FMAv4f32:
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RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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"fma\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set (v4f32 VECREG:$rT),
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(fadd (v4f32 VECREG:$rC),
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(fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
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def FMAf32:
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RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
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"fma\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
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// FP multiply and subtract
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// Subtracts value in rC from product
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// res = a * b - c
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def FMSv4f32 :
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RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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"fms\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set (v4f32 VECREG:$rT),
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(fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
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(v4f32 VECREG:$rC)))]>;
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def FMSf32 :
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RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
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"fms\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set R32FP:$rT,
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(fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
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// Floating Negative Mulitply and Subtract
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// Subtracts product from value in rC
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// res = fneg(fms a b c)
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// = - (a * b - c)
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// = c - a * b
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// NOTE: subtraction order
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// fsub a b = a - b
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// fs a b = b - a?
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def FNMSf32 :
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RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
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"fnms\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
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def FNMSv4f32 :
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RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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"fnms\t$rT, $rA, $rB, $rC", SPrecFP,
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[(set (v4f32 VECREG:$rT),
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(fsub (v4f32 VECREG:$rC),
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(fmul (v4f32 VECREG:$rA),
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(v4f32 VECREG:$rB))))]>;
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//--------------------------------------
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// Floating Point Conversions
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// Signed conversions:
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@ -394,7 +394,7 @@ def R8C : RegisterClass<"SPU", [i8], 128,
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// The SPU's registers as vector registers:
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def VECREG : RegisterClass<"SPU",
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[v16i8,v8i16,v2i32,v4i32,v4f32,v2i64,v2f64],
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[v16i8,v8i16,v2i32,v2f32,v4i32,v4f32,v2i64,v2f64],
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128,
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[
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/* volatile register */
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35
test/CodeGen/CellSPU/v2f32.ll
Normal file
35
test/CodeGen/CellSPU/v2f32.ll
Normal file
@ -0,0 +1,35 @@
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;RUN: llc --march=cellspu %s -o - | FileCheck %s
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%vec = type <2 x float>
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define %vec @test_ret(%vec %param)
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{
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;CHECK: bi $lr
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ret %vec %param
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}
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define %vec @test_add(%vec %param)
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{
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;CHECK: fa $3, $3, $3
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%1 = fadd %vec %param, %param
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;CHECK: bi $lr
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ret %vec %1
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}
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define %vec @test_sub(%vec %param)
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{
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;CHECK: fs $3, $3, $3
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%1 = fsub %vec %param, %param
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;CHECK: bi $lr
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ret %vec %1
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}
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define %vec @test_mul(%vec %param)
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{
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;CHECK: fm $3, $3, $3
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%1 = fmul %vec %param, %param
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;CHECK: bi $lr
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ret %vec %1
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}
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