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[SimplifyCFG] Cost required selects
Before we speculatively execute a basic block, query the cost of inserting the necessary select instructions against the phi folding threshold. For non-trivial insertions, a more accurate decision can probably be made during machine if-conversion. With minsize we query the CodeSize cost, otherwise we use SizeAndLatency. Differential Revision: https://reviews.llvm.org/D82438
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@ -2042,6 +2042,25 @@ bool SimplifyCFGOpt::SpeculativelyExecuteBB(BranchInst *BI, BasicBlock *ThenBB,
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BasicBlock *BB = BI->getParent();
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BasicBlock *EndBB = ThenBB->getTerminator()->getSuccessor(0);
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TargetTransformInfo::TargetCostKind CostKind =
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BI->getFunction()->hasMinSize() ?
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TargetTransformInfo::TCK_CodeSize :
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TargetTransformInfo::TCK_SizeAndLatency;
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// Check how expensive it will be to insert the necessary selects.
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unsigned CostOfSelects = 0;
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for (PHINode &PN : EndBB->phis()) {
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unsigned OrigI = PN.getBasicBlockIndex(BB);
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unsigned ThenI = PN.getBasicBlockIndex(ThenBB);
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Value *OrigV = PN.getIncomingValue(OrigI);
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Value *ThenV = PN.getIncomingValue(ThenI);
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if (OrigV != ThenV)
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CostOfSelects +=
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TTI.getCmpSelInstrCost(Instruction::Select, PN.getType(), nullptr,
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CostKind);
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}
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if (CostOfSelects > PHINodeFoldingThreshold * TargetTransformInfo::TCC_Basic)
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return false;
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// If ThenBB is actually on the false edge of the conditional branch, remember
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// to swap the select operands later.
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bool Invert = false;
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@ -6,6 +6,7 @@
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; Test that the phis from for.inc.preheader aren't hoisted into sw.bb92 because
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; the cost is too great - we can make a better decision later on.
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; FIXME: The Arm cost model needs to be updated for SizeAndLatency.
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define i32 @multiple_spec_select_costs(i8* %a, i32* %idx, i8 %in) {
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; V8M-LABEL: @multiple_spec_select_costs(
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; V8M-NEXT: entry:
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@ -113,13 +114,13 @@ define i32 @multiple_spec_select_costs_minsize(i8* %a, i32* %idx, i8 %in) #0 {
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; V8M: sw.bb92:
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; V8M-NEXT: [[C_OFF_I150:%.*]] = add i8 [[IN]], -48
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; V8M-NEXT: [[UGT_9:%.*]] = icmp ugt i8 [[C_OFF_I150]], 9
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; V8M-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[UGT_9]], i1 false, i1 true
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; V8M-NEXT: [[SPEC_SELECT1:%.*]] = select i1 [[UGT_9]], i32 1, i32 7
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; V8M-NEXT: br i1 [[UGT_9]], label [[FOR_INC_PREHEADER]], label [[SELECT_UNFOLD198:%.*]]
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; V8M: select.unfold198:
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; V8M-NEXT: br label [[FOR_INC_PREHEADER]]
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; V8M: for.inc.preheader:
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; V8M-NEXT: [[STR_PH_0:%.*]] = phi i8* [ [[GEP_A_2]], [[ENTRY:%.*]] ], [ [[INCDEC_PTR109_C4]], [[SW_BB92]] ]
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; V8M-NEXT: [[CMP:%.*]] = phi i1 [ false, [[ENTRY]] ], [ [[SPEC_SELECT]], [[SW_BB92]] ]
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; V8M-NEXT: [[PHI_RES:%.*]] = phi i32 [ 1, [[ENTRY]] ], [ [[SPEC_SELECT1]], [[SW_BB92]] ]
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; V8M-NEXT: [[STR_PH_0:%.*]] = phi i8* [ [[INCDEC_PTR109_C4]], [[SELECT_UNFOLD198]] ], [ [[INCDEC_PTR109_C4]], [[SW_BB92]] ], [ [[GEP_A_2]], [[ENTRY:%.*]] ]
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; V8M-NEXT: [[CMP:%.*]] = phi i1 [ true, [[SELECT_UNFOLD198]] ], [ false, [[SW_BB92]] ], [ false, [[ENTRY]] ]
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; V8M-NEXT: [[PHI_RES:%.*]] = phi i32 [ 7, [[SELECT_UNFOLD198]] ], [ 1, [[SW_BB92]] ], [ 1, [[ENTRY]] ]
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; V8M-NEXT: br label [[FOR_INC:%.*]]
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; V8M: for.inc:
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; V8M-NEXT: [[STR_PH_1:%.*]] = phi i8* [ [[INCDEC_PTR109:%.*]], [[FOR_BODY:%.*]] ], [ [[STR_PH_0]], [[FOR_INC_PREHEADER]] ]
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