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[PPC64LE] More vector swap optimization TLC
This makes one substantive change and a few stylistic changes to the VSX swap optimization pass. The substantive change is to permit LXSDX and LXSSPX instructions to participate in swap optimization computations. The previous change to insert a swap following a SUBREG_TO_REG widening operation makes this almost trivial. I experimented with also permitting STXSDX and STXSSPX instructions. This can be done using similar techniques: we could insert a swap prior to a narrowing COPY operation, and then permit these stores to participate. I prototyped this, but discovered that the pattern of a narrowing COPY followed by an STXSDX does not occur in any of our test-suite code. So instead, I added commentary indicating that this could be done. Other TLC: - I changed SH_COPYSCALAR to SH_COPYWIDEN to more clearly indicate the direction of the copy. - I factored the insertion of swap instructions into a separate function. Finally, I added a new test case to check that the scalar-to-vector loads are working properly with swap optimization. llvm-svn: 242838
This commit is contained in:
Bill Schmidt
parent
be5ba86160
commit
76e220a5ef
@ -94,7 +94,7 @@ enum SHValues {
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SH_NOSWAP_ST,
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SH_SPLAT,
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SH_XXPERMDI,
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SH_COPYSCALAR
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SH_COPYWIDEN
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};
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struct PPCVSXSwapRemoval : public MachineFunctionPass {
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@ -149,6 +149,11 @@ private:
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// handling. Return true iff any changes are made.
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bool removeSwaps();
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// Insert a swap instruction from SrcReg to DstReg at the given
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// InsertPoint.
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void insertSwap(MachineInstr *MI, MachineBasicBlock::iterator InsertPoint,
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unsigned DstReg, unsigned SrcReg);
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// Update instructions requiring special handling.
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void handleSpecialSwappables(int EntryIdx);
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@ -340,6 +345,15 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
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SwapVector[VecIdx].IsLoad = 1;
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SwapVector[VecIdx].IsSwap = 1;
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break;
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case PPC::LXSDX:
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case PPC::LXSSPX:
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// A load of a floating-point value into the high-order half of
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// a vector register is safe, provided that we introduce a swap
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// following the load, which will be done by the SUBREG_TO_REG
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// support. So just mark these as safe.
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SwapVector[VecIdx].IsLoad = 1;
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SwapVector[VecIdx].IsSwappable = 1;
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break;
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case PPC::STVX:
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// Non-permuting stores are currently unsafe. We can use special
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// handling for this in the future. By not marking these as
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@ -382,7 +396,7 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
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else if (isVecReg(MI.getOperand(0).getReg()) &&
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isScalarVecReg(MI.getOperand(2).getReg())) {
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SwapVector[VecIdx].IsSwappable = 1;
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SwapVector[VecIdx].SpecialHandling = SHValues::SH_COPYSCALAR;
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SwapVector[VecIdx].SpecialHandling = SHValues::SH_COPYWIDEN;
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}
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break;
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}
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@ -417,7 +431,14 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
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case PPC::STVEHX:
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case PPC::STVEWX:
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case PPC::STVXL:
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// We can handle STXSDX and STXSSPX similarly to LXSDX and LXSSPX,
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// by adding special handling for narrowing copies as well as
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// widening ones. However, I've experimented with this, and in
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// practice we currently do not appear to use STXSDX fed by
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// a narrowing copy from a full vector register. Since I can't
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// generate any useful test cases, I've left this alone for now.
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case PPC::STXSDX:
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case PPC::STXSSPX:
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case PPC::VCIPHER:
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case PPC::VCIPHERLAST:
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case PPC::VMRGHB:
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@ -540,7 +561,8 @@ unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg,
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}
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if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg)) {
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SwapVector[VecIdx].MentionsPhysVR = 1;
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if (!isScalarVecReg(CopySrcReg))
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SwapVector[VecIdx].MentionsPhysVR = 1;
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return CopySrcReg;
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}
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@ -626,8 +648,8 @@ void PPCVSXSwapRemoval::recordUnoptimizableWebs() {
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SwapVector[Repr].WebRejected = 1;
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DEBUG(dbgs() <<
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format("Web %d rejected for physreg, partial reg, or not swap[pable]\n",
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Repr));
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format("Web %d rejected for physreg, partial reg, or not "
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"swap[pable]\n", Repr));
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DEBUG(dbgs() << " in " << EntryIdx << ": ");
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DEBUG(SwapVector[EntryIdx].VSEMI->dump());
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DEBUG(dbgs() << "\n");
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@ -740,6 +762,21 @@ void PPCVSXSwapRemoval::markSwapsForRemoval() {
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}
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}
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// Create an xxswapd instruction and insert it prior to the given point.
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// MI is used to determine basic block and debug loc information.
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// FIXME: When inserting a swap, we should check whether SrcReg is
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// defined by another swap: SrcReg = XXPERMDI Reg, Reg, 2; If so,
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// then instead we should generate a copy from Reg to DstReg.
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void PPCVSXSwapRemoval::insertSwap(MachineInstr *MI,
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MachineBasicBlock::iterator InsertPoint,
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unsigned DstReg, unsigned SrcReg) {
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BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
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TII->get(PPC::XXPERMDI), DstReg)
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.addReg(SrcReg)
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.addReg(SrcReg)
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.addImm(2);
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}
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// The identified swap entry requires special handling to allow its
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// containing computation to be optimized. Perform that handling
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// here.
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@ -808,7 +845,7 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
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// For a copy from a scalar floating-point register to a vector
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// register, removing swaps will leave the copied value in the
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// wrong lane. Insert a swap following the copy to fix this.
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case SHValues::SH_COPYSCALAR: {
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case SHValues::SH_COPYWIDEN: {
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MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
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DEBUG(dbgs() << "Changing SUBREG_TO_REG: ");
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@ -829,7 +866,6 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
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// assignment problem. In this case we must copy from VRRC to VSRC
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// prior to the swap, and from VSRC to VRRC following the swap.
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// Coalescing will usually remove all this mess.
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if (DstRC == &PPC::VRRCRegClass) {
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unsigned VSRCTmp1 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
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unsigned VSRCTmp2 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
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@ -839,11 +875,7 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
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.addReg(NewVReg);
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DEBUG(MI->getNextNode()->dump());
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BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
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TII->get(PPC::XXPERMDI), VSRCTmp2)
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.addReg(VSRCTmp1)
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.addReg(VSRCTmp1)
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.addImm(2);
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insertSwap(MI, InsertPoint, VSRCTmp2, VSRCTmp1);
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DEBUG(MI->getNextNode()->getNextNode()->dump());
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BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
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@ -852,13 +884,7 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
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DEBUG(MI->getNextNode()->getNextNode()->getNextNode()->dump());
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} else {
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BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
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TII->get(PPC::XXPERMDI), DstReg)
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.addReg(NewVReg)
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.addReg(NewVReg)
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.addImm(2);
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insertSwap(MI, InsertPoint, DstReg, NewVReg);
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DEBUG(MI->getNextNode()->dump());
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}
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break;
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@ -944,8 +970,8 @@ void PPCVSXSwapRemoval::dumpSwapVector() {
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case SH_XXPERMDI:
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DEBUG(dbgs() << "special:xxpermdi ");
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break;
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case SH_COPYSCALAR:
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DEBUG(dbgs() << "special:copyscalar ");
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case SH_COPYWIDEN:
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DEBUG(dbgs() << "special:copywiden ");
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break;
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}
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}
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44
test/CodeGen/PowerPC/swaps-le-6.ll
Normal file
44
test/CodeGen/PowerPC/swaps-le-6.ll
Normal file
@ -0,0 +1,44 @@
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
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; These tests verify that VSX swap optimization works when loading a scalar
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; into a vector register.
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@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
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@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
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@y = global double 1.780000e+00, align 8
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define void @bar0() {
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 0
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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; CHECK-LABEL: @bar0
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; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
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; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
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; CHECK: xxswapd [[REG3:[0-9]+]], [[REG2]]
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; CHECK: xxspltd [[REG4:[0-9]+]], [[REG3]], 1
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; CHECK: xxpermdi [[REG5:[0-9]+]], [[REG4]], [[REG1]], 1
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; CHECK: stxvd2x [[REG5]]
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define void @bar1() {
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 1
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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; CHECK-LABEL: @bar1
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; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
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; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
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; CHECK: xxswapd [[REG3:[0-9]+]], [[REG2]]
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; CHECK: xxspltd [[REG4:[0-9]+]], [[REG3]], 1
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; CHECK: xxmrghd [[REG5:[0-9]+]], [[REG1]], [[REG4]]
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; CHECK: stxvd2x [[REG5]]
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