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PR4340: Run SimplifyDemandedVectorElts on insertelement instructions;

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sometimes it can find simplifications that won't be found otherwise.

llvm-svn: 73006
This commit is contained in:
Eli Friedman 2009-06-06 20:08:03 +00:00
parent cf715254c7
commit 770f633389
2 changed files with 20 additions and 0 deletions
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6
lib/Transforms/Scalar/InstructionCombining.cpp
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@ -12579,6 +12579,12 @@ Instruction *InstCombiner::visitInsertElementInst(InsertElementInst &IE) {
}
}
unsigned VWidth = cast<VectorType>(VecOp->getType())->getNumElements();
APInt UndefElts(VWidth, 0);
APInt AllOnesEltMask(APInt::getAllOnesValue(VWidth));
if (SimplifyDemandedVectorElts(&IE, AllOnesEltMask, UndefElts))
return &IE;
return 0;
}

14
test/Transforms/InstCombine/vec_demanded_elts-3.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep load
; PR4340
define void @vac(<4 x float>* nocapture %a) nounwind {
entry:
%tmp1 = load <4 x float>* %a ; <<4 x float>> [#uses=1]
%vecins = insertelement <4 x float> %tmp1, float 0.000000e+00, i32 0 ; <<4 x float>> [#uses=1]
%vecins4 = insertelement <4 x float> %vecins, float 0.000000e+00, i32 1; <<4 x float>> [#uses=1]
%vecins6 = insertelement <4 x float> %vecins4, float 0.000000e+00, i32 2; <<4 x float>> [#uses=1]
%vecins8 = insertelement <4 x float> %vecins6, float 0.000000e+00, i32 3; <<4 x float>> [#uses=1]
store <4 x float> %vecins8, <4 x float>* %a
ret void
}