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ARM vmrs system registers mvfr0 and mvfr1 handling.

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rdar://11058464

llvm-svn: 152881
This commit is contained in:
Jim Grosbach 2012-03-16 00:27:18 +00:00
parent 40cd87af9e
commit 77151885af
3 changed files with 18 additions and 3 deletions
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4
lib/Target/ARM/ARMInstrVFP.td
View File

@ -1212,6 +1212,10 @@ let Uses = [FPSCR] in {
"vmrs", "\t$Rt, fpexc", []>;
def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
"vmrs", "\t$Rt, fpsid", []>;
def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
"vmrs", "\t$Rt, mvfr0", []>;
def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
"vmrs", "\t$Rt, mvfr1", []>;
}
//===----------------------------------------------------------------------===//

2
lib/Target/ARM/ARMRegisterInfo.td
View File

@ -166,6 +166,8 @@ def ITSTATE : ARMReg<4, "itstate">;
// Special Registers - only available in privileged mode.
def FPSID : ARMReg<0, "fpsid">;
def MVFR1 : ARMReg<6, "mvfr1">;
def MVFR0 : ARMReg<7, "mvfr0">;
def FPEXC : ARMReg<8, "fpexc">;
// Register classes.

15
test/MC/ARM/simple-fp-encoding.s
View File

@ -120,12 +120,21 @@
@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
vnmls.f32 s1, s2, s0
@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
vmrs APSR_nzcv, fpscr
vmrs apsr_nzcv, fpscr
fmstat
vmrs r2, fpsid
vmrs r3, FPSID
vmrs r4, mvfr0
vmrs r5, MVFR1
@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
@ CHECK: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
@ CHECK: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
@ CHECK: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
@ CHECK: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
vnegne.f64 d16, d16