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Batch 5 of Mips CodeGen tests
llvm-svn: 54510
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12
test/CodeGen/Mips/2008-07-29-icmp.ll
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test/CodeGen/Mips/2008-07-29-icmp.ll
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; RUN: llvm-as < %s | llc -enable-legalize-types -march=mips | \
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; RUN: grep {b\[ne\]\[eq\]} | count 1
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "mipsallegrexel-psp-elf"
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define float @A(float %a, float %b, i32 %j) nounwind {
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entry:
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icmp sgt i32 %j, 1 ; <i1>:0 [#uses=1]
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%.0 = select i1 %0, float %a, float %b ; <float> [#uses=1]
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ret float %.0
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}
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test/CodeGen/Mips/2008-07-31-fcopysign.ll
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test/CodeGen/Mips/2008-07-31-fcopysign.ll
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; RUN: llvm-as < %s | llc -enable-legalize-types -march=mips -f -o %t
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; RUN: grep abs.s %t | count 1
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; RUN: grep neg.s %t | count 1
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "mipsallegrexel-psp-elf"
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define float @A(float %i, float %j) nounwind {
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entry:
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tail call float @copysignf( float %i, float %j ) nounwind readnone ; <float>:0 [#uses=1]
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ret float %0
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}
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declare float @copysignf(float, float) nounwind readnone
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test/CodeGen/Mips/2008-08-01-AsmInline.ll
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test/CodeGen/Mips/2008-08-01-AsmInline.ll
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; RUN: llvm-as < %s | llc -enable-legalize-types -march=mips -f -o %t
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; RUN: grep mfhi %t | count 1
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; RUN: grep mflo %t | count 1
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; RUN: grep multu %t | count 1
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "mipsallegrexel-psp-elf"
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%struct.DWstruct = type { i32, i32 }
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define i32 @A0(i32 %u, i32 %v) nounwind {
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entry:
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%asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwind
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%asmresult = extractvalue %struct.DWstruct %asmtmp, 0
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%asmresult1 = extractvalue %struct.DWstruct %asmtmp, 1 ; <i32> [#uses=1]
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%res = add i32 %asmresult, %asmresult1
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ret i32 %res
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}
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