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Remove trailing whitespace

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llvm-svn: 21420
This commit is contained in:
Misha Brukman 2005-04-21 22:36:52 +00:00
parent aec3b563b0
commit 774e55c446
37 changed files with 299 additions and 299 deletions
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12
lib/CodeGen/AsmPrinter.cpp
View File

@ -148,7 +148,7 @@ static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
O << "\""; O << "\"";
for (unsigned i = 0; i != CVA->getNumOperands(); ++i) { for (unsigned i = 0; i != CVA->getNumOperands(); ++i) {
unsigned char C = unsigned char C =
(unsigned char)cast<ConstantInt>(CVA->getOperand(i))->getRawValue(); (unsigned char)cast<ConstantInt>(CVA->getOperand(i))->getRawValue();
if (C == '"') { if (C == '"') {
@ -178,7 +178,7 @@ static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
/// emitGlobalConstant - Print a general LLVM constant to the .s file. /// emitGlobalConstant - Print a general LLVM constant to the .s file.
/// ///
void AsmPrinter::emitGlobalConstant(const Constant *CV) { void AsmPrinter::emitGlobalConstant(const Constant *CV) {
const TargetData &TD = TM.getTargetData(); const TargetData &TD = TM.getTargetData();
if (CV->isNullValue() || isa<UndefValue>(CV)) { if (CV->isNullValue() || isa<UndefValue>(CV)) {
@ -253,7 +253,7 @@ void AsmPrinter::emitGlobalConstant(const Constant *CV) {
int32_t UVal; int32_t UVal;
} U; } U;
U.FVal = (float)Val; U.FVal = (float)Val;
O << Data32bitsDirective << U.UVal << "\t" << CommentString O << Data32bitsDirective << U.UVal << "\t" << CommentString
<< " float " << Val << "\n"; << " float " << Val << "\n";
return; return;
@ -261,7 +261,7 @@ void AsmPrinter::emitGlobalConstant(const Constant *CV) {
} else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) { } else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) {
if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
uint64_t Val = CI->getRawValue(); uint64_t Val = CI->getRawValue();
if (Data64bitsDirective) if (Data64bitsDirective)
O << Data64bitsDirective << Val << "\n"; O << Data64bitsDirective << Val << "\n";
else if (TD.isBigEndian()) { else if (TD.isBigEndian()) {
@ -285,7 +285,7 @@ void AsmPrinter::emitGlobalConstant(const Constant *CV) {
const Type *type = CV->getType(); const Type *type = CV->getType();
switch (type->getTypeID()) { switch (type->getTypeID()) {
case Type::BoolTyID: case Type::BoolTyID:
case Type::UByteTyID: case Type::SByteTyID: case Type::UByteTyID: case Type::SByteTyID:
O << Data8bitsDirective; O << Data8bitsDirective;
break; break;
@ -301,7 +301,7 @@ void AsmPrinter::emitGlobalConstant(const Constant *CV) {
case Type::UIntTyID: case Type::IntTyID: case Type::UIntTyID: case Type::IntTyID:
O << Data32bitsDirective; O << Data32bitsDirective;
break; break;
case Type::ULongTyID: case Type::LongTyID: case Type::ULongTyID: case Type::LongTyID:
assert (0 && "Should have already output double-word constant."); assert (0 && "Should have already output double-word constant.");
case Type::FloatTyID: case Type::DoubleTyID: case Type::FloatTyID: case Type::DoubleTyID:
assert (0 && "Should have already output floating point constant."); assert (0 && "Should have already output floating point constant.");

6
lib/CodeGen/BranchFolding.cpp
View File

@ -1,10 +1,10 @@
//===-- BranchFolding.cpp - Fold machine code branch instructions ---------===// //===-- BranchFolding.cpp - Fold machine code branch instructions ---------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This pass forwards branches to unconditional branches to make them branch // This pass forwards branches to unconditional branches to make them branch
@ -158,7 +158,7 @@ bool BranchFolder::OptimizeBlock(MachineFunction::iterator MBB,
assert(Br->getNumOperands() == 1 && Br->getOperand(0).isMachineBasicBlock() assert(Br->getNumOperands() == 1 && Br->getOperand(0).isMachineBasicBlock()
&& "Uncond branch should take one MBB argument!"); && "Uncond branch should take one MBB argument!");
MachineBasicBlock *Dest = Br->getOperand(0).getMachineBasicBlock(); MachineBasicBlock *Dest = Br->getOperand(0).getMachineBasicBlock();
while (!MBB->pred_empty()) { while (!MBB->pred_empty()) {
MachineBasicBlock *Pred = *(MBB->pred_end()-1); MachineBasicBlock *Pred = *(MBB->pred_end()-1);
ReplaceUsesOfBlockWith(Pred, MBB, Dest, TII); ReplaceUsesOfBlockWith(Pred, MBB, Dest, TII);

12
lib/CodeGen/IntrinsicLowering.cpp
View File

@ -1,10 +1,10 @@
//===-- IntrinsicLowering.cpp - Intrinsic Lowering default implementation -===// //===-- IntrinsicLowering.cpp - Intrinsic Lowering default implementation -===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the default intrinsic lowering implementation. // This file implements the default intrinsic lowering implementation.
@ -117,7 +117,7 @@ void DefaultIntrinsicLowering::AddPrototypes(Module &M) {
void DefaultIntrinsicLowering::LowerIntrinsicCall(CallInst *CI) { void DefaultIntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
Function *Callee = CI->getCalledFunction(); Function *Callee = CI->getCalledFunction();
assert(Callee && "Cannot lower an indirect call!"); assert(Callee && "Cannot lower an indirect call!");
switch (Callee->getIntrinsicID()) { switch (Callee->getIntrinsicID()) {
case Intrinsic::not_intrinsic: case Intrinsic::not_intrinsic:
std::cerr << "Cannot lower a call to a non-intrinsic function '" std::cerr << "Cannot lower a call to a non-intrinsic function '"
@ -140,7 +140,7 @@ void DefaultIntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
CI->replaceAllUsesWith(V); CI->replaceAllUsesWith(V);
break; break;
} }
case Intrinsic::sigsetjmp: case Intrinsic::sigsetjmp:
if (CI->getType() != Type::VoidTy) if (CI->getType() != Type::VoidTy)
CI->replaceAllUsesWith(Constant::getNullValue(CI->getType())); CI->replaceAllUsesWith(Constant::getNullValue(CI->getType()));
break; break;
@ -163,7 +163,7 @@ void DefaultIntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
case Intrinsic::returnaddress: case Intrinsic::returnaddress:
case Intrinsic::frameaddress: case Intrinsic::frameaddress:
std::cerr << "WARNING: this target does not support the llvm." std::cerr << "WARNING: this target does not support the llvm."
<< (Callee->getIntrinsicID() == Intrinsic::returnaddress ? << (Callee->getIntrinsicID() == Intrinsic::returnaddress ?
"return" : "frame") << "address intrinsic.\n"; "return" : "frame") << "address intrinsic.\n";
CI->replaceAllUsesWith(ConstantPointerNull::get( CI->replaceAllUsesWith(ConstantPointerNull::get(
cast<PointerType>(CI->getType()))); cast<PointerType>(CI->getType())));
@ -220,7 +220,7 @@ void DefaultIntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
break; break;
} }
} }
assert(CI->use_empty() && assert(CI->use_empty() &&
"Lowering should have eliminated any uses of the intrinsic call!"); "Lowering should have eliminated any uses of the intrinsic call!");
CI->getParent()->getInstList().erase(CI); CI->getParent()->getInstList().erase(CI);

4
lib/CodeGen/LiveInterval.cpp
View File

@ -34,7 +34,7 @@ using namespace llvm;
// //
bool LiveInterval::liveAt(unsigned I) const { bool LiveInterval::liveAt(unsigned I) const {
Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I); Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
if (r == ranges.begin()) if (r == ranges.begin())
return false; return false;
@ -174,7 +174,7 @@ void LiveInterval::extendIntervalEndTo(Ranges::iterator I, unsigned NewEnd) {
/// extendIntervalStartTo - This method is used when we want to extend the range /// extendIntervalStartTo - This method is used when we want to extend the range
/// specified by I to start at the specified endpoint. To do this, we should /// specified by I to start at the specified endpoint. To do this, we should
/// merge and eliminate all ranges that this will overlap with. /// merge and eliminate all ranges that this will overlap with.
LiveInterval::Ranges::iterator LiveInterval::Ranges::iterator
LiveInterval::extendIntervalStartTo(Ranges::iterator I, unsigned NewStart) { LiveInterval::extendIntervalStartTo(Ranges::iterator I, unsigned NewStart) {
assert(I != ranges.end() && "Not a valid interval!"); assert(I != ranges.end() && "Not a valid interval!");
unsigned ValId = I->ValId; unsigned ValId = I->ValId;

4
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -742,7 +742,7 @@ bool LiveIntervals::differingRegisterClasses(unsigned RegA,
// Get the register classes for the first reg. // Get the register classes for the first reg.
if (MRegisterInfo::isPhysicalRegister(RegA)) { if (MRegisterInfo::isPhysicalRegister(RegA)) {
assert(MRegisterInfo::isVirtualRegister(RegB) && assert(MRegisterInfo::isVirtualRegister(RegB) &&
"Shouldn't consider two physregs!"); "Shouldn't consider two physregs!");
return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
} }
@ -775,7 +775,7 @@ bool LiveIntervals::overlapsAliases(const LiveInterval *LHS,
} }
LiveInterval LiveIntervals::createInterval(unsigned reg) { LiveInterval LiveIntervals::createInterval(unsigned reg) {
float Weight = MRegisterInfo::isPhysicalRegister(reg) ? float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
(float)HUGE_VAL :0.0F; (float)HUGE_VAL :0.0F;
return LiveInterval(reg, Weight); return LiveInterval(reg, Weight);
} }

20
lib/CodeGen/LiveVariables.cpp
View File

@ -1,12 +1,12 @@
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===// //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the LiveVariable analysis pass. For each machine // This file implements the LiveVariable analysis pass. For each machine
// instruction in the function, this pass calculates the set of registers that // instruction in the function, this pass calculates the set of registers that
// are immediately dead after the instruction (i.e., the instruction calculates // are immediately dead after the instruction (i.e., the instruction calculates
@ -98,7 +98,7 @@ void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!"); assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
#endif #endif
assert(MBB != VRInfo.DefInst->getParent() && assert(MBB != VRInfo.DefInst->getParent() &&
"Should have kill for defblock!"); "Should have kill for defblock!");
// Add a new kill entry for this basic block. // Add a new kill entry for this basic block.
@ -156,7 +156,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// physical register. This is a purely local property, because all physical // physical register. This is a purely local property, because all physical
// register references as presumed dead across basic blocks. // register references as presumed dead across basic blocks.
// //
PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) * PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
RegInfo->getNumRegs()); RegInfo->getNumRegs());
PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs()); PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0); std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
@ -171,7 +171,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
"Cannot have a live-in virtual register!"); "Cannot have a live-in virtual register!");
HandlePhysRegDef(*I, 0); HandlePhysRegDef(*I, 0);
} }
// Calculate live variable information in depth first order on the CFG of the // Calculate live variable information in depth first order on the CFG of the
// function. This guarantees that we will see the definition of a virtual // function. This guarantees that we will see the definition of a virtual
// register before its uses due to dominance properties of SSA (except for PHI // register before its uses due to dominance properties of SSA (except for PHI
@ -195,7 +195,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// Unless it is a PHI node. In this case, ONLY process the DEF, not any // Unless it is a PHI node. In this case, ONLY process the DEF, not any
// of the uses. They will be handled in other basic blocks. // of the uses. They will be handled in other basic blocks.
if (MI->getOpcode() == TargetInstrInfo::PHI) if (MI->getOpcode() == TargetInstrInfo::PHI)
NumOperandsToProcess = 1; NumOperandsToProcess = 1;
// Loop over implicit uses, using them. // Loop over implicit uses, using them.
@ -247,7 +247,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
E = MBB->succ_end(); SI != E; ++SI) { E = MBB->succ_end(); SI != E; ++SI) {
MachineBasicBlock *Succ = *SI; MachineBasicBlock *Succ = *SI;
// PHI nodes are guaranteed to be at the top of the block... // PHI nodes are guaranteed to be at the top of the block...
for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end(); for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) { MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
@ -267,7 +267,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
} }
} }
} }
// Finally, if the last block in the function is a return, make sure to mark // Finally, if the last block in the function is a return, make sure to mark
// it as using all of the live-out values in the function. // it as using all of the live-out values in the function.
if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) { if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
@ -305,7 +305,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// function. If so, it is due to a bug in the instruction selector or some // function. If so, it is due to a bug in the instruction selector or some
// other part of the code generator if this happens. // other part of the code generator if this happens.
#ifndef NDEBUG #ifndef NDEBUG
for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i) for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
assert(Visited.count(&*i) != 0 && "unreachable basic block found"); assert(Visited.count(&*i) != 0 && "unreachable basic block found");
#endif #endif

2
lib/CodeGen/MachineBasicBlock.cpp
View File

@ -133,7 +133,7 @@ void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
} }
void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) { void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
std::vector<MachineBasicBlock *>::iterator I = std::vector<MachineBasicBlock *>::iterator I =
std::find(Predecessors.begin(), Predecessors.end(), pred); std::find(Predecessors.begin(), Predecessors.end(), pred);
assert(I != Predecessors.end() && "Pred is not a predecessor of this block!"); assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
Predecessors.erase(I); Predecessors.erase(I);

14
lib/CodeGen/MachineCodeEmitter.cpp
View File

@ -1,10 +1,10 @@
//===-- MachineCodeEmitter.cpp - Implement the MachineCodeEmitter itf -----===// //===-- MachineCodeEmitter.cpp - Implement the MachineCodeEmitter itf -----===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the MachineCodeEmitter interface. // This file implements the MachineCodeEmitter interface.
@ -35,7 +35,7 @@ namespace {
std::cout << "\n--- End of stub for Function\n"; std::cout << "\n--- End of stub for Function\n";
return 0; return 0;
} }
void emitByte(unsigned char B) { void emitByte(unsigned char B) {
std::cout << "0x" << std::hex << (unsigned int)B << std::dec << " "; std::cout << "0x" << std::hex << (unsigned int)B << std::dec << " ";
} }
@ -62,14 +62,14 @@ namespace {
MachineCodeEmitter &MCE; MachineCodeEmitter &MCE;
unsigned counter; unsigned counter;
unsigned values[4]; unsigned values[4];
public: public:
FilePrinterEmitter(MachineCodeEmitter &M, std::ostream &os) FilePrinterEmitter(MachineCodeEmitter &M, std::ostream &os)
: o(os), MCE(M), counter(0) { : o(os), MCE(M), counter(0) {
openActual(); openActual();
} }
~FilePrinterEmitter() { ~FilePrinterEmitter() {
o << "\n"; o << "\n";
actual.close(); actual.close();
} }
@ -101,7 +101,7 @@ namespace {
void *finishFunctionStub(const Function *F) { void *finishFunctionStub(const Function *F) {
return MCE.finishFunctionStub(F); return MCE.finishFunctionStub(F);
} }
void emitByte(unsigned char B) { void emitByte(unsigned char B) {
MCE.emitByte(B); MCE.emitByte(B);
actual << B; actual.flush(); actual << B; actual.flush();

2
lib/CodeGen/MachineFunction.cpp
View File

@ -256,7 +256,7 @@ void MachineFunction::clearSSARegMap() {
/// CreateStackObject - Create a stack object for a value of the specified type. /// CreateStackObject - Create a stack object for a value of the specified type.
/// ///
int MachineFrameInfo::CreateStackObject(const Type *Ty, const TargetData &TD) { int MachineFrameInfo::CreateStackObject(const Type *Ty, const TargetData &TD) {
return CreateStackObject((unsigned)TD.getTypeSize(Ty), return CreateStackObject((unsigned)TD.getTypeSize(Ty),
TD.getTypeAlignment(Ty)); TD.getTypeAlignment(Ty));
} }

36
lib/CodeGen/MachineInstr.cpp
View File

@ -1,10 +1,10 @@
//===-- MachineInstr.cpp --------------------------------------------------===// //===-- MachineInstr.cpp --------------------------------------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Methods common to all machine instructions. // Methods common to all machine instructions.
@ -28,7 +28,7 @@ using namespace llvm;
// Global variable holding an array of descriptors for machine instructions. // Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine. // The actual object needs to be created separately for each target machine.
// This variable is initialized and reset by class TargetInstrInfo. // This variable is initialized and reset by class TargetInstrInfo.
// //
// FIXME: This should be a property of the target so that more than one target // FIXME: This should be a property of the target so that more than one target
// at a time can be active... // at a time can be active...
// //
@ -112,7 +112,7 @@ bool MachineInstr::OperandsComplete() const {
/// replace - Support for replacing opcode and operands of a MachineInstr in /// replace - Support for replacing opcode and operands of a MachineInstr in
/// place. This only resets the size of the operand vector and initializes it. /// place. This only resets the size of the operand vector and initializes it.
/// The new operands must be set explicitly later. /// The new operands must be set explicitly later.
/// ///
void MachineInstr::replace(short opcode, unsigned numOperands) { void MachineInstr::replace(short opcode, unsigned numOperands) {
assert(getNumImplicitRefs() == 0 && assert(getNumImplicitRefs() == 0 &&
"This is probably broken because implicit refs are going to be lost."); "This is probably broken because implicit refs are going to be lost.");
@ -178,7 +178,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
{ {
assert((!defsOnly || !notDefsAndUses) && assert((!defsOnly || !notDefsAndUses) &&
"notDefsAndUses is irrelevant if defsOnly == true."); "notDefsAndUses is irrelevant if defsOnly == true.");
unsigned numSubst = 0; unsigned numSubst = 0;
// Substitute operands // Substitute operands
@ -236,7 +236,7 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
static void print(const MachineOperand &MO, std::ostream &OS, static void print(const MachineOperand &MO, std::ostream &OS,
const TargetMachine *TM) { const TargetMachine *TM) {
const MRegisterInfo *MRI = 0; const MRegisterInfo *MRI = 0;
if (TM) MRI = TM->getRegisterInfo(); if (TM) MRI = TM->getRegisterInfo();
bool CloseParen = true; bool CloseParen = true;
@ -250,7 +250,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
OS << "%hm("; OS << "%hm(";
else else
CloseParen = false; CloseParen = false;
switch (MO.getType()) { switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister: case MachineOperand::MO_VirtualRegister:
if (MO.getVRegValue()) { if (MO.getVRegValue()) {
@ -333,21 +333,21 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
// be attached to a Machine function yet // be attached to a Machine function yet
if (TM) if (TM)
OS << TM->getInstrInfo()->getName(getOpcode()); OS << TM->getInstrInfo()->getName(getOpcode());
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i); const MachineOperand& mop = getOperand(i);
if (i != StartOp) if (i != StartOp)
OS << ","; OS << ",";
OS << " "; OS << " ";
::print(mop, OS, TM); ::print(mop, OS, TM);
if (mop.isDef()) if (mop.isDef())
if (mop.isUse()) if (mop.isUse())
OS << "<def&use>"; OS << "<def&use>";
else else
OS << "<def>"; OS << "<def>";
} }
// code for printing implicit references // code for printing implicit references
if (getNumImplicitRefs()) { if (getNumImplicitRefs()) {
OS << "\tImplicitRefs: "; OS << "\tImplicitRefs: ";
@ -361,7 +361,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
OS << "<def>"; OS << "<def>";
} }
} }
OS << "\n"; OS << "\n";
} }
@ -381,7 +381,7 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
// Otherwise, print it out in the "raw" format without symbolic register names // Otherwise, print it out in the "raw" format without symbolic register names
// and such. // and such.
os << TargetInstrDescriptors[MI.getOpcode()].Name; os << TargetInstrDescriptors[MI.getOpcode()].Name;
for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) { for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
os << "\t" << MI.getOperand(i); os << "\t" << MI.getOperand(i);
if (MI.getOperand(i).isDef()) if (MI.getOperand(i).isDef())
@ -390,13 +390,13 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
else else
os << "<d>"; os << "<d>";
} }
// code for printing implicit references // code for printing implicit references
unsigned NumOfImpRefs = MI.getNumImplicitRefs(); unsigned NumOfImpRefs = MI.getNumImplicitRefs();
if (NumOfImpRefs > 0) { if (NumOfImpRefs > 0) {
os << "\tImplicit: "; os << "\tImplicit: ";
for (unsigned z = 0; z < NumOfImpRefs; z++) { for (unsigned z = 0; z < NumOfImpRefs; z++) {
OutputValue(os, MI.getImplicitRef(z)); OutputValue(os, MI.getImplicitRef(z));
if (MI.getImplicitOp(z).isDef()) if (MI.getImplicitOp(z).isDef())
if (MI.getImplicitOp(z).isUse()) if (MI.getImplicitOp(z).isUse())
os << "<d&u>"; os << "<d&u>";
@ -405,7 +405,7 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
os << "\t"; os << "\t";
} }
} }
return os << "\n"; return os << "\n";
} }
@ -418,7 +418,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
OS << "%hh("; OS << "%hh(";
else if (MO.isLoBits64()) else if (MO.isLoBits64())
OS << "%hm("; OS << "%hm(";
switch (MO.getType()) { switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister: case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg()) if (MO.hasAllocatedReg())
@ -479,10 +479,10 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
assert(0 && "Unrecognized operand type"); assert(0 && "Unrecognized operand type");
break; break;
} }
if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64()) if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
OS << ")"; OS << ")";
return OS; return OS;
} }

28
lib/CodeGen/PHIElimination.cpp
View File

@ -1,10 +1,10 @@
//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===// //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This pass eliminates machine instruction PHI nodes by inserting copy // This pass eliminates machine instruction PHI nodes by inserting copy
@ -97,12 +97,12 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
while (MBB.front().getOpcode() == TargetInstrInfo::PHI) { while (MBB.front().getOpcode() == TargetInstrInfo::PHI) {
// Unlink the PHI node from the basic block, but don't delete the PHI yet. // Unlink the PHI node from the basic block, but don't delete the PHI yet.
MachineInstr *MPhi = MBB.remove(MBB.begin()); MachineInstr *MPhi = MBB.remove(MBB.begin());
assert(MRegisterInfo::isVirtualRegister(MPhi->getOperand(0).getReg()) && assert(MRegisterInfo::isVirtualRegister(MPhi->getOperand(0).getReg()) &&
"PHI node doesn't write virt reg?"); "PHI node doesn't write virt reg?");
unsigned DestReg = MPhi->getOperand(0).getReg(); unsigned DestReg = MPhi->getOperand(0).getReg();
// Create a new register for the incoming PHI arguments // Create a new register for the incoming PHI arguments
const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg); const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC); unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
@ -112,7 +112,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
// into the phi node destination. // into the phi node destination.
// //
RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC); RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
// Update live variable information if there is any... // Update live variable information if there is any...
if (LV) { if (LV) {
MachineInstr *PHICopy = prior(AfterPHIsIt); MachineInstr *PHICopy = prior(AfterPHIsIt);
@ -128,7 +128,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
// of any registers, or if the value itself is dead, we need to move this // of any registers, or if the value itself is dead, we need to move this
// information over to the new copy we just inserted. // information over to the new copy we just inserted.
// //
std::pair<LiveVariables::killed_iterator, LiveVariables::killed_iterator> std::pair<LiveVariables::killed_iterator, LiveVariables::killed_iterator>
RKs = LV->killed_range(MPhi); RKs = LV->killed_range(MPhi);
std::vector<std::pair<MachineInstr*, unsigned> > Range; std::vector<std::pair<MachineInstr*, unsigned> > Range;
if (RKs.first != RKs.second) // Delete the range. if (RKs.first != RKs.second) // Delete the range.
@ -154,13 +154,13 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
// //
for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) { for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) {
MachineOperand &opVal = MPhi->getOperand(i-1); MachineOperand &opVal = MPhi->getOperand(i-1);
// Get the MachineBasicBlock equivalent of the BasicBlock that is the // Get the MachineBasicBlock equivalent of the BasicBlock that is the
// source path the PHI. // source path the PHI.
MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMachineBasicBlock(); MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMachineBasicBlock();
MachineBasicBlock::iterator I = opBlock.getFirstTerminator(); MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
// Check to make sure we haven't already emitted the copy for this block. // Check to make sure we haven't already emitted the copy for this block.
// This can happen because PHI nodes may have multiple entries for the // This can happen because PHI nodes may have multiple entries for the
// same basic block. It doesn't matter which entry we use though, because // same basic block. It doesn't matter which entry we use though, because
@ -171,7 +171,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
// register we are interested in! // register we are interested in!
// //
bool HaveNotEmitted = true; bool HaveNotEmitted = true;
if (I != opBlock.begin()) { if (I != opBlock.begin()) {
MachineBasicBlock::iterator PrevInst = prior(I); MachineBasicBlock::iterator PrevInst = prior(I);
for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
@ -180,7 +180,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
if (MO.isDef()) { if (MO.isDef()) {
HaveNotEmitted = false; HaveNotEmitted = false;
break; break;
} }
} }
} }
@ -215,7 +215,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(), for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) { E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) {
MachineBasicBlock *SuccMBB = *SI; MachineBasicBlock *SuccMBB = *SI;
// Is it alive in this successor? // Is it alive in this successor?
unsigned SuccIdx = SuccMBB->getNumber(); unsigned SuccIdx = SuccMBB->getNumber();
if (SuccIdx < InRegVI.AliveBlocks.size() && if (SuccIdx < InRegVI.AliveBlocks.size() &&
@ -223,7 +223,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
ValueIsLive = true; ValueIsLive = true;
break; break;
} }
// Is it killed in this successor? // Is it killed in this successor?
for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
if (InRegVI.Kills[i]->getParent() == SuccMBB) { if (InRegVI.Kills[i]->getParent() == SuccMBB) {
@ -235,7 +235,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
if (!ValueIsLive) if (!ValueIsLive)
ValueIsLive = VRegPHIUseCount[SrcReg] != 0; ValueIsLive = VRegPHIUseCount[SrcReg] != 0;
} }
// Okay, if we now know that the value is not live out of the block, // Okay, if we now know that the value is not live out of the block,
// we can add a kill marker to the copy we inserted saying that it // we can add a kill marker to the copy we inserted saying that it
// kills the incoming value! // kills the incoming value!
@ -252,7 +252,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
} }
} }
} }
// Really delete the PHI instruction now! // Really delete the PHI instruction now!
delete MPhi; delete MPhi;
} }

4
lib/CodeGen/Passes.cpp
View File

@ -1,10 +1,10 @@
//===-- Passes.cpp - Target independent code generation passes ------------===// //===-- Passes.cpp - Target independent code generation passes ------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file defines interfaces to access the target independent code // This file defines interfaces to access the target independent code

24
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -1,10 +1,10 @@
//===-- PrologEpilogInserter.cpp - Insert Prolog/Epilog code in function --===// //===-- PrologEpilogInserter.cpp - Insert Prolog/Epilog code in function --===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This pass is responsible for finalizing the functions frame layout, saving // This pass is responsible for finalizing the functions frame layout, saving
@ -190,7 +190,7 @@ void PEI::calculateCallerSavedRegisters(MachineFunction &Fn) {
void PEI::saveCallerSavedRegisters(MachineFunction &Fn) { void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
// Early exit if no caller saved registers are modified! // Early exit if no caller saved registers are modified!
if (RegsToSave.empty()) if (RegsToSave.empty())
return; return;
const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
@ -226,10 +226,10 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
/// ///
void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo(); const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
bool StackGrowsDown = bool StackGrowsDown =
TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown; TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
// Loop over all of the stack objects, assigning sequential addresses... // Loop over all of the stack objects, assigning sequential addresses...
MachineFrameInfo *FFI = Fn.getFrameInfo(); MachineFrameInfo *FFI = Fn.getFrameInfo();
@ -241,12 +241,12 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
int Offset = TFI.getOffsetOfLocalArea(); int Offset = TFI.getOffsetOfLocalArea();
if (StackGrowsDown) if (StackGrowsDown)
Offset = -Offset; Offset = -Offset;
assert(Offset >= 0 assert(Offset >= 0
&& "Local area offset should be in direction of stack growth"); && "Local area offset should be in direction of stack growth");
// If there are fixed sized objects that are preallocated in the local area, // If there are fixed sized objects that are preallocated in the local area,
// non-fixed objects can't be allocated right at the start of local area. // non-fixed objects can't be allocated right at the start of local area.
// We currently don't support filling in holes in between fixed sized objects, // We currently don't support filling in holes in between fixed sized objects,
// so we adjust 'Offset' to point to the end of last fixed sized // so we adjust 'Offset' to point to the end of last fixed sized
// preallocated object. // preallocated object.
for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
@ -257,11 +257,11 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
// the offset is negative, so we negate the offset to get the distance. // the offset is negative, so we negate the offset to get the distance.
FixedOff = -FFI->getObjectOffset(i); FixedOff = -FFI->getObjectOffset(i);
} else { } else {
// The maximum distance from the start pointer is at the upper // The maximum distance from the start pointer is at the upper
// address of the object. // address of the object.
FixedOff = FFI->getObjectOffset(i) + FFI->getObjectSize(i); FixedOff = FFI->getObjectOffset(i) + FFI->getObjectSize(i);
} }
if (FixedOff > Offset) Offset = FixedOff; if (FixedOff > Offset) Offset = FixedOff;
} }
for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
@ -274,11 +274,11 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
assert(Align <= StackAlignment && "Cannot align stack object to higher " assert(Align <= StackAlignment && "Cannot align stack object to higher "
"alignment boundary than the stack itself!"); "alignment boundary than the stack itself!");
Offset = (Offset+Align-1)/Align*Align; // Adjust to Alignment boundary... Offset = (Offset+Align-1)/Align*Align; // Adjust to Alignment boundary...
if (StackGrowsDown) { if (StackGrowsDown) {
FFI->setObjectOffset(i, -Offset); // Set the computed offset FFI->setObjectOffset(i, -Offset); // Set the computed offset
} else { } else {
FFI->setObjectOffset(i, Offset); FFI->setObjectOffset(i, Offset);
Offset += FFI->getObjectSize(i); Offset += FFI->getObjectSize(i);
} }
} }

8
lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -208,7 +208,7 @@ void RA::linearScan()
assert(MRegisterInfo::isVirtualRegister(cur->reg) && assert(MRegisterInfo::isVirtualRegister(cur->reg) &&
"Can only allocate virtual registers!"); "Can only allocate virtual registers!");
// Allocating a virtual register. try to find a free // Allocating a virtual register. try to find a free
// physical register or spill an interval (possibly this one) in order to // physical register or spill an interval (possibly this one) in order to
// assign it one. // assign it one.
@ -266,7 +266,7 @@ void RA::processActiveIntervals(unsigned CurPoint)
active_[i] = active_.back(); active_[i] = active_.back();
active_.pop_back(); active_.pop_back();
--i; --e; --i; --e;
} else if (IntervalPos->start > CurPoint) { } else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list. // Move inactive intervals to inactive list.
DEBUG(std::cerr << "\t\tinterval " << *Interval << " inactive\n"); DEBUG(std::cerr << "\t\tinterval " << *Interval << " inactive\n");
@ -300,7 +300,7 @@ void RA::processInactiveIntervals(unsigned CurPoint)
unsigned reg = Interval->reg; unsigned reg = Interval->reg;
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint); IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
if (IntervalPos == Interval->end()) { // remove expired intervals. if (IntervalPos == Interval->end()) { // remove expired intervals.
DEBUG(std::cerr << "\t\tinterval " << *Interval << " expired\n"); DEBUG(std::cerr << "\t\tinterval " << *Interval << " expired\n");
@ -331,7 +331,7 @@ void RA::processInactiveIntervals(unsigned CurPoint)
/// updateSpillWeights - updates the spill weights of the specifed physical /// updateSpillWeights - updates the spill weights of the specifed physical
/// register and its weight. /// register and its weight.
static void updateSpillWeights(std::vector<float> &Weights, static void updateSpillWeights(std::vector<float> &Weights,
unsigned reg, float weight, unsigned reg, float weight,
const MRegisterInfo *MRI) { const MRegisterInfo *MRI) {
Weights[reg] += weight; Weights[reg] += weight;

2
lib/CodeGen/RegAllocLocal.cpp
View File

@ -210,7 +210,7 @@ namespace {
/// ///
MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum); unsigned OpNum);
void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
unsigned PhysReg); unsigned PhysReg);

24
lib/CodeGen/RegAllocSimple.cpp
View File

@ -1,10 +1,10 @@
//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===// //===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements a simple register allocator. *Very* simple: It immediate // This file implements a simple register allocator. *Very* simple: It immediate
@ -36,7 +36,7 @@ namespace {
const TargetMachine *TM; const TargetMachine *TM;
const MRegisterInfo *RegInfo; const MRegisterInfo *RegInfo;
bool *PhysRegsEverUsed; bool *PhysRegsEverUsed;
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled // these values are spilled
std::map<unsigned, int> StackSlotForVirtReg; std::map<unsigned, int> StackSlotForVirtReg;
@ -102,7 +102,7 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
// Allocate a new stack object for this spill location... // Allocate a new stack object for this spill location...
int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(), int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
RC->getAlignment()); RC->getAlignment());
// Assign the slot... // Assign the slot...
StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
@ -115,10 +115,10 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
while (1) { while (1) {
unsigned regIdx = RegClassIdx[RC]++; unsigned regIdx = RegClassIdx[RC]++;
assert(RI+regIdx != RE && "Not enough registers!"); assert(RI+regIdx != RE && "Not enough registers!");
unsigned PhysReg = *(RI+regIdx); unsigned PhysReg = *(RI+regIdx);
if (!RegsUsed[PhysReg]) { if (!RegsUsed[PhysReg]) {
PhysRegsEverUsed[PhysReg] = true; PhysRegsEverUsed[PhysReg] = true;
return PhysReg; return PhysReg;
@ -158,7 +158,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
std::map<unsigned, unsigned> Virt2PhysRegMap; std::map<unsigned, unsigned> Virt2PhysRegMap;
RegsUsed.resize(RegInfo->getNumRegs()); RegsUsed.resize(RegInfo->getNumRegs());
// This is a preliminary pass that will invalidate any registers that are // This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses). // used by the instruction (including implicit uses).
unsigned Opcode = MI->getOpcode(); unsigned Opcode = MI->getOpcode();
@ -166,23 +166,23 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
const unsigned *Regs; const unsigned *Regs;
for (Regs = Desc.ImplicitUses; *Regs; ++Regs) for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
RegsUsed[*Regs] = true; RegsUsed[*Regs] = true;
for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) { for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
RegsUsed[*Regs] = true; RegsUsed[*Regs] = true;
PhysRegsEverUsed[*Regs] = true; PhysRegsEverUsed[*Regs] = true;
} }
// Loop over uses, move from memory into registers. // Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) { for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i); MachineOperand &op = MI->getOperand(i);
if (op.isRegister() && op.getReg() && if (op.isRegister() && op.getReg() &&
MRegisterInfo::isVirtualRegister(op.getReg())) { MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg(); unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n"); DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: "; DEBUG(std::cerr << "\t inst[" << i << "]: ";
MI->print(std::cerr, TM)); MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical // make sure the same virtual register maps to the same physical
// register in any given instruction // register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg]; unsigned physReg = Virt2PhysRegMap[virtualReg];
@ -211,7 +211,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
} }
} }
MI->SetMachineOperandReg(i, physReg); MI->SetMachineOperandReg(i, physReg);
DEBUG(std::cerr << "virt: " << virtualReg << DEBUG(std::cerr << "virt: " << virtualReg <<
", phys: " << op.getReg() << "\n"); ", phys: " << op.getReg() << "\n");
} }
} }

82
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -1,10 +1,10 @@
//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the SelectionDAG::Legalize method. // This file implements the SelectionDAG::Legalize method.
@ -285,7 +285,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
VT = MVT::f32; VT = MVT::f32;
Extend = true; Extend = true;
} }
SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC), SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC),
TLI.getPointerTy()); TLI.getPointerTy());
if (Extend) { if (Extend) {
@ -433,7 +433,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2); Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2);
else else
Result = SDOperand(Node, 0); Result = SDOperand(Node, 0);
// Since loads produce two values, make sure to remember that we legalized // Since loads produce two values, make sure to remember that we legalized
// both of them. // both of them.
AddLegalizedOperand(SDOperand(Node, 0), Result); AddLegalizedOperand(SDOperand(Node, 0), Result);
@ -458,7 +458,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
AddLegalizedOperand(SDOperand(Node, 0), Result); AddLegalizedOperand(SDOperand(Node, 0), Result);
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo); return Result.getValue(Op.ResNo);
case TargetLowering::Legal: case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) || if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(1)) Tmp2 != Node->getOperand(1))
@ -504,7 +504,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case ISD::CopyToReg: case ISD::CopyToReg:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
switch (getTypeAction(Node->getOperand(1).getValueType())) { switch (getTypeAction(Node->getOperand(1).getValueType())) {
case Legal: case Legal:
// Legalize the incoming value (must be legal). // Legalize the incoming value (must be legal).
@ -518,7 +518,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break; break;
case Expand: case Expand:
SDOperand Lo, Hi; SDOperand Lo, Hi;
ExpandOp(Node->getOperand(1), Lo, Hi); ExpandOp(Node->getOperand(1), Lo, Hi);
unsigned Reg = cast<RegSDNode>(Node)->getReg(); unsigned Reg = cast<RegSDNode>(Node)->getReg();
Lo = DAG.getCopyToReg(Tmp1, Lo, Reg); Lo = DAG.getCopyToReg(Tmp1, Lo, Reg);
Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1); Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1);
@ -544,7 +544,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
SDOperand Lo, Hi; SDOperand Lo, Hi;
ExpandOp(Node->getOperand(1), Lo, Hi); ExpandOp(Node->getOperand(1), Lo, Hi);
Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
break; break;
} }
case Promote: case Promote:
Tmp2 = PromoteOp(Node->getOperand(1)); Tmp2 = PromoteOp(Node->getOperand(1));
@ -569,7 +569,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
ExpandOp(Node->getOperand(i), Lo, Hi); ExpandOp(Node->getOperand(i), Lo, Hi);
NewValues.push_back(Lo); NewValues.push_back(Lo);
NewValues.push_back(Hi); NewValues.push_back(Hi);
break; break;
} }
case Promote: case Promote:
assert(0 && "Can't promote multiple return value yet!"); assert(0 && "Can't promote multiple return value yet!");
@ -753,7 +753,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
Node->getValueType(0), Tmp1, Tmp2); Node->getValueType(0), Tmp1, Tmp2);
break; break;
case Expand: case Expand:
SDOperand LHSLo, LHSHi, RHSLo, RHSHi; SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
ExpandOp(Node->getOperand(0), LHSLo, LHSHi); ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
ExpandOp(Node->getOperand(1), RHSLo, RHSHi); ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
@ -765,15 +765,15 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
if (RHSCST->isAllOnesValue()) { if (RHSCST->isAllOnesValue()) {
// Comparison to -1. // Comparison to -1.
Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
Node->getValueType(0), Tmp1, RHSLo); Node->getValueType(0), Tmp1, RHSLo);
break; break;
} }
Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
Node->getValueType(0), Tmp1, Node->getValueType(0), Tmp1,
DAG.getConstant(0, Tmp1.getValueType())); DAG.getConstant(0, Tmp1.getValueType()));
break; break;
@ -781,7 +781,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
// If this is a comparison of the sign bit, just look at the top part. // If this is a comparison of the sign bit, just look at the top part.
// X > -1, x < 0 // X > -1, x < 0
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT && if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT &&
CST->getValue() == 0) || // X < 0 CST->getValue() == 0) || // X < 0
(cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT && (cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT &&
(CST->isAllOnesValue()))) // X > -1 (CST->isAllOnesValue()))) // X > -1
@ -801,7 +801,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case ISD::SETGE: case ISD::SETGE:
case ISD::SETUGE: LowCC = ISD::SETUGE; break; case ISD::SETUGE: LowCC = ISD::SETUGE; break;
} }
// Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
// Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
// dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
@ -836,7 +836,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break; break;
} }
} else { } else {
Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
} }
SDOperand Tmp4; SDOperand Tmp4;
@ -956,7 +956,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Tmp2 != Node->getOperand(1)) Tmp2 != Node->getOperand(1))
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
break; break;
case ISD::UREM: case ISD::UREM:
case ISD::SREM: case ISD::SREM:
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
@ -965,7 +965,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case TargetLowering::Legal: case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) || if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(1)) Tmp2 != Node->getOperand(1))
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
Tmp2); Tmp2);
break; break;
case TargetLowering::Promote: case TargetLowering::Promote:
@ -1042,7 +1042,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
// In the expand case, we must be dealing with a truncate, because // In the expand case, we must be dealing with a truncate, because
// otherwise the result would be larger than the source. // otherwise the result would be larger than the source.
ExpandOp(Node->getOperand(0), Tmp1, Tmp2); ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
// Since the result is legal, we should just be able to truncate the low // Since the result is legal, we should just be able to truncate the low
// part of the source. // part of the source.
Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
@ -1134,7 +1134,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
int SSFI = int SSFI =
MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
@ -1231,7 +1231,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
case Expand: case Expand:
ExpandOp(Node->getOperand(0), Tmp1, Tmp2); ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
// Truncate the low part of the expanded value to the result type // Truncate the low part of the expanded value to the result type
Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1); Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1);
} }
break; break;
case ISD::SIGN_EXTEND: case ISD::SIGN_EXTEND:
@ -1445,7 +1445,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
// Insert the new chain mapping. // Insert the new chain mapping.
AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
break; break;
} }
} }
assert(Result.Val && "Didn't set a result!"); assert(Result.Val && "Didn't set a result!");
@ -1568,16 +1568,16 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
return true; return true;
case ISD::SRA: case ISD::SRA:
if (Cst > VTBits) { if (Cst > VTBits) {
Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy)); DAG.getConstant(NVTBits-1, ShTy));
} else if (Cst > NVTBits) { } else if (Cst > NVTBits) {
Lo = DAG.getNode(ISD::SRA, NVT, InH, Lo = DAG.getNode(ISD::SRA, NVT, InH,
DAG.getConstant(Cst-NVTBits, ShTy)); DAG.getConstant(Cst-NVTBits, ShTy));
Hi = DAG.getNode(ISD::SRA, NVT, InH, Hi = DAG.getNode(ISD::SRA, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy)); DAG.getConstant(NVTBits-1, ShTy));
} else if (Cst == NVTBits) { } else if (Cst == NVTBits) {
Lo = InH; Lo = InH;
Hi = DAG.getNode(ISD::SRA, NVT, InH, Hi = DAG.getNode(ISD::SRA, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy)); DAG.getConstant(NVTBits-1, ShTy));
} else { } else {
Lo = DAG.getNode(ISD::OR, NVT, Lo = DAG.getNode(ISD::OR, NVT,
@ -1620,7 +1620,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
DAG.getNode(ISD::SHL, NVT, InH, ShAmt), DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
DAG.getNode(ISD::SRL, NVT, InL, NAmt)); DAG.getNode(ISD::SRL, NVT, InL, NAmt));
SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
} else { } else {
@ -1705,14 +1705,14 @@ static SDNode *FindAdjCallStackUp(SDNode *Node) {
if (Node->hasOneUse()) // Simple case, only has one user to check. if (Node->hasOneUse()) // Simple case, only has one user to check.
return FindAdjCallStackUp(*Node->use_begin()); return FindAdjCallStackUp(*Node->use_begin());
SDOperand TheChain(Node, Node->getNumValues()-1); SDOperand TheChain(Node, Node->getNumValues()-1);
assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!"); assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!");
for (SDNode::use_iterator UI = Node->use_begin(), for (SDNode::use_iterator UI = Node->use_begin(),
E = Node->use_end(); ; ++UI) { E = Node->use_end(); ; ++UI) {
assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!"); assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!");
// Make sure to only follow users of our token chain. // Make sure to only follow users of our token chain.
SDNode *User = *UI; SDNode *User = *UI;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
@ -1732,7 +1732,7 @@ static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
SDNode *LatestAdjCallStackUp = 0; SDNode *LatestAdjCallStackUp = 0;
FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown); FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown);
//std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n"; //std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n";
// It is possible that no ISD::ADJCALLSTACKDOWN was found because there is no // It is possible that no ISD::ADJCALLSTACKDOWN was found because there is no
// previous call in the function. LatestCallStackDown may in that case be // previous call in the function. LatestCallStackDown may in that case be
// the entry node itself. Do not attempt to find a matching ADJCALLSTACKUP // the entry node itself. Do not attempt to find a matching ADJCALLSTACKUP
@ -1742,12 +1742,12 @@ static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
else else
LatestAdjCallStackUp = Entry.Val; LatestAdjCallStackUp = Entry.Val;
assert(LatestAdjCallStackUp && "NULL return from FindAdjCallStackUp"); assert(LatestAdjCallStackUp && "NULL return from FindAdjCallStackUp");
SDNode *EarliestAdjCallStackUp = 0; SDNode *EarliestAdjCallStackUp = 0;
FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp); FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp);
if (EarliestAdjCallStackUp) { if (EarliestAdjCallStackUp) {
//std::cerr << "Found node: "; //std::cerr << "Found node: ";
//EarliestAdjCallStackUp->dump(); std::cerr <<"\n"; //EarliestAdjCallStackUp->dump(); std::cerr <<"\n";
} }
@ -1775,7 +1775,7 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
} }
SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
// We don't care about token chains for libcalls. We just use the entry // We don't care about token chains for libcalls. We just use the entry
// node as our input and ignore the output chain. This allows us to place // node as our input and ignore the output chain. This allows us to place
// calls wherever we need them to satisfy data dependences. // calls wherever we need them to satisfy data dependences.
@ -1866,7 +1866,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
const Type *RetTy = MVT::getTypeForValueType(DestTy); const Type *RetTy = MVT::getTypeForValueType(DestTy);
return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first; return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first;
} }
/// ExpandOp - Expand the specified SDOperand into its two component pieces /// ExpandOp - Expand the specified SDOperand into its two component pieces
@ -1922,7 +1922,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
// Aggregate register values are always in consequtive pairs. // Aggregate register values are always in consequtive pairs.
Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0)); Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0));
Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1)); Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1));
// Remember that we legalized the chain. // Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
@ -1953,7 +1953,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
// other one. // other one.
SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
Hi.getValue(1)); Hi.getValue(1));
// Remember that we legalized the chain. // Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), TF); AddLegalizedOperand(Op.getValue(1), TF);
if (!TLI.isLittleEndian()) if (!TLI.isLittleEndian())
@ -2031,7 +2031,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
// The low part is just a sign extension of the input (which degenerates to // The low part is just a sign extension of the input (which degenerates to
// a copy). // a copy).
Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
// The high part is obtained by SRA'ing all but one of the bits of the lo // The high part is obtained by SRA'ing all but one of the bits of the lo
// part. // part.
unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
@ -2054,7 +2054,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
// The low part is just a zero extension of the input (which degenerates to // The low part is just a zero extension of the input (which degenerates to
// a copy). // a copy).
Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
// The high part is just a zero. // The high part is just a zero.
Hi = DAG.getConstant(0, NVT); Hi = DAG.getConstant(0, NVT);
break; break;
@ -2121,7 +2121,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
Lo = ExpandLibCall("__lshrdi3", Node, Hi); Lo = ExpandLibCall("__lshrdi3", Node, Hi);
break; break;
case ISD::ADD: case ISD::ADD:
ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
Lo, Hi); Lo, Hi);
break; break;

62
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1,10 +1,10 @@
//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// //===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This implements the SelectionDAG class. // This implements the SelectionDAG class.
@ -60,7 +60,7 @@ static bool isInvertibleForFree(SDOperand N) {
if (isa<ConstantSDNode>(N.Val)) return true; if (isa<ConstantSDNode>(N.Val)) return true;
if (isa<SetCCSDNode>(N.Val) && N.Val->hasOneUse()) if (isa<SetCCSDNode>(N.Val) && N.Val->hasOneUse())
return true; return true;
return false; return false;
} }
@ -118,9 +118,9 @@ ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
// Cannot fold a signed integer setcc with an unsigned integer setcc. // Cannot fold a signed integer setcc with an unsigned integer setcc.
return ISD::SETCC_INVALID; return ISD::SETCC_INVALID;
unsigned Op = Op1 | Op2; // Combine all of the condition bits. unsigned Op = Op1 | Op2; // Combine all of the condition bits.
// If the N and U bits get set then the resultant comparison DOES suddenly // If the N and U bits get set then the resultant comparison DOES suddenly
// care about orderedness, and is true when ordered. // care about orderedness, and is true when ordered.
if (Op > ISD::SETTRUE2) if (Op > ISD::SETTRUE2)
@ -136,7 +136,7 @@ ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
bool isInteger) { bool isInteger) {
if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
// Cannot fold a signed setcc with an unsigned setcc. // Cannot fold a signed setcc with an unsigned setcc.
return ISD::SETCC_INVALID; return ISD::SETCC_INVALID;
// Combine all of the condition bits. // Combine all of the condition bits.
return ISD::CondCode(Op1 & Op2); return ISD::CondCode(Op1 & Op2);
@ -269,7 +269,7 @@ void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) {
// Now that we removed this operand, see if there are no uses of it left. // Now that we removed this operand, see if there are no uses of it left.
DeleteNodeIfDead(O, NodeSet); DeleteNodeIfDead(O, NodeSet);
} }
// Remove the node from the nodes set and delete it. // Remove the node from the nodes set and delete it.
std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet;
AllNodeSet.erase(N); AllNodeSet.erase(N);
@ -297,7 +297,7 @@ SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) {
// Mask out any bits that are not valid for this constant. // Mask out any bits that are not valid for this constant.
if (VT != MVT::i64) if (VT != MVT::i64)
Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1;
SDNode *&N = Constants[std::make_pair(Val, VT)]; SDNode *&N = Constants[std::make_pair(Val, VT)];
if (N) return SDOperand(N, 0); if (N) return SDOperand(N, 0);
N = new ConstantSDNode(Val, VT); N = new ConstantSDNode(Val, VT);
@ -317,7 +317,7 @@ SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) {
double DV; double DV;
uint64_t IV; uint64_t IV;
}; };
DV = Val; DV = Val;
SDNode *&N = ConstantFPs[std::make_pair(IV, VT)]; SDNode *&N = ConstantFPs[std::make_pair(IV, VT)];
@ -385,7 +385,7 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
uint64_t C2 = N2C->getValue(); uint64_t C2 = N2C->getValue();
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
uint64_t C1 = N1C->getValue(); uint64_t C1 = N1C->getValue();
// Sign extend the operands if required // Sign extend the operands if required
if (ISD::isSignedIntSetCC(Cond)) { if (ISD::isSignedIntSetCC(Cond)) {
C1 = N1C->getSignExtended(); C1 = N1C->getSignExtended();
@ -480,14 +480,14 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
N2 = getConstant(C2, N2.getValueType()); N2 = getConstant(C2, N2.getValueType());
N2C = cast<ConstantSDNode>(N2.Val); N2C = cast<ConstantSDNode>(N2.Val);
} }
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal)
return getConstant(0, VT); // X < MIN --> false return getConstant(0, VT); // X < MIN --> false
// Canonicalize setgt X, Min --> setne X, Min // Canonicalize setgt X, Min --> setne X, Min
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal)
return getSetCC(ISD::SETNE, VT, N1, N2); return getSetCC(ISD::SETNE, VT, N1, N2);
// If we have setult X, 1, turn it into seteq X, 0 // If we have setult X, 1, turn it into seteq X, 0
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1)
return getSetCC(ISD::SETEQ, VT, N1, return getSetCC(ISD::SETEQ, VT, N1,
@ -538,7 +538,7 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val))
if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) {
double C1 = N1C->getValue(), C2 = N2C->getValue(); double C1 = N1C->getValue(), C2 = N2C->getValue();
switch (Cond) { switch (Cond) {
default: break; // FIXME: Implement the rest of these! default: break; // FIXME: Implement the rest of these!
case ISD::SETEQ: return getConstant(C1 == C2, VT); case ISD::SETEQ: return getConstant(C1 == C2, VT);
@ -588,7 +588,7 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
} }
// FIXME: move this stuff to the DAG Combiner when it exists! // FIXME: move this stuff to the DAG Combiner when it exists!
// Simplify (X+Z) == X --> Z == 0 // Simplify (X+Z) == X --> Z == 0
if (N1.getOperand(0) == N2) if (N1.getOperand(0) == N2)
return getSetCC(Cond, VT, N1.getOperand(1), return getSetCC(Cond, VT, N1.getOperand(1),
@ -601,7 +601,7 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
// (Z-X) == X --> Z == X<<1 // (Z-X) == X --> Z == X<<1
return getSetCC(Cond, VT, N1.getOperand(0), return getSetCC(Cond, VT, N1.getOperand(0),
getNode(ISD::SHL, N2.getValueType(), getNode(ISD::SHL, N2.getValueType(),
N2, getConstant(1, TLI.getShiftAmountTy()))); N2, getConstant(1, TLI.getShiftAmountTy())));
} }
} }
@ -760,7 +760,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
const TargetLowering &TLI) { const TargetLowering &TLI) {
unsigned SrcBits; unsigned SrcBits;
if (Mask == 0) return true; if (Mask == 0) return true;
// If we know the result of a setcc has the top bits zero, use this info. // If we know the result of a setcc has the top bits zero, use this info.
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
case ISD::UNDEF: case ISD::UNDEF:
@ -769,7 +769,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
case ISD::SETCC: case ISD::SETCC:
return ((Mask & 1) == 0) && return ((Mask & 1) == 0) &&
TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
case ISD::ZEXTLOAD: case ISD::ZEXTLOAD:
@ -1066,7 +1066,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
Op2 == LHS->getCondition() && MVT::isInteger(LL.getValueType())) { Op2 == LHS->getCondition() && MVT::isInteger(LL.getValueType())) {
if ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || if ((Op2 == ISD::SETEQ && Opcode == ISD::AND) ||
(Op2 == ISD::SETNE && Opcode == ISD::OR)) (Op2 == ISD::SETNE && Opcode == ISD::OR))
return getSetCC(Op2, VT, return getSetCC(Op2, VT,
getNode(ISD::OR, LR.getValueType(), LL, RL), LR); getNode(ISD::OR, LR.getValueType(), LL, RL), LR);
} }
@ -1075,7 +1075,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
Op2 = ISD::getSetCCSwappedOperands(Op2); Op2 = ISD::getSetCCSwappedOperands(Op2);
goto MatchedBackwards; goto MatchedBackwards;
} }
if (LL == RL && LR == RR) { if (LL == RL && LR == RR) {
MatchedBackwards: MatchedBackwards:
ISD::CondCode Result; ISD::CondCode Result;
@ -1179,7 +1179,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
if (N1C) if (N1C)
if (N1C->getValue()) if (N1C->getValue())
return N2; // select true, X, Y -> X return N2; // select true, X, Y -> X
else else
return N3; // select false, X, Y -> Y return N3; // select false, X, Y -> Y
if (N2 == N3) return N2; // select C, X, X -> X if (N2 == N3) return N2; // select C, X, X -> X
@ -1275,7 +1275,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
SDNode *N = new SDNode(Opcode, N1, N2, N3); SDNode *N = new SDNode(Opcode, N1, N2, N3);
switch (Opcode) { switch (Opcode) {
default: default:
N->setValueTypes(VT); N->setValueTypes(VT);
break; break;
case ISD::DYNAMIC_STACKALLOC: // DYNAMIC_STACKALLOC produces pointer and chain case ISD::DYNAMIC_STACKALLOC: // DYNAMIC_STACKALLOC produces pointer and chain
@ -1371,7 +1371,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
// If we are extending the result of a setcc, and we already know the // If we are extending the result of a setcc, and we already know the
// contents of the top bits, eliminate the extension. // contents of the top bits, eliminate the extension.
if (N1.getOpcode() == ISD::SETCC && if (N1.getOpcode() == ISD::SETCC &&
TLI.getSetCCResultContents() == TLI.getSetCCResultContents() ==
TargetLowering::ZeroOrNegativeOneSetCCResult) TargetLowering::ZeroOrNegativeOneSetCCResult)
return N1; return N1;
@ -1412,7 +1412,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
if (VT == EVT) if (VT == EVT)
return getNode(ISD::LOAD, VT, N1, N2); return getNode(ISD::LOAD, VT, N1, N2);
assert(EVT < VT && "Should only be an extending load, not truncating!"); assert(EVT < VT && "Should only be an extending load, not truncating!");
assert((Opcode == ISD::EXTLOAD || MVT::isInteger(VT)) && assert((Opcode == ISD::EXTLOAD || MVT::isInteger(VT)) &&
"Cannot sign/zero extend a FP load!"); "Cannot sign/zero extend a FP load!");
assert(MVT::isInteger(VT) == MVT::isInteger(EVT) && assert(MVT::isInteger(VT) == MVT::isInteger(EVT) &&
"Cannot convert from FP to Int or Int -> FP!"); "Cannot convert from FP to Int or Int -> FP!");
@ -1444,7 +1444,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
if (isa<Constant>(N1)) { if (isa<Constant>(N1)) {
SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1);
if (isa<Constant>(Op)) if (isa<Constant>(Op))
N1 = Op; N1 = Op;
} }
// Also for ConstantFP? // Also for ConstantFP?
#endif #endif
@ -1599,8 +1599,8 @@ const char *SDNode::getOperationName() const {
case ISD::SETOLT: return "setcc:setolt"; case ISD::SETOLT: return "setcc:setolt";
case ISD::SETOLE: return "setcc:setole"; case ISD::SETOLE: return "setcc:setole";
case ISD::SETONE: return "setcc:setone"; case ISD::SETONE: return "setcc:setone";
case ISD::SETO: return "setcc:seto"; case ISD::SETO: return "setcc:seto";
case ISD::SETUO: return "setcc:setuo"; case ISD::SETUO: return "setcc:setuo";
case ISD::SETUEQ: return "setcc:setue"; case ISD::SETUEQ: return "setcc:setue";
case ISD::SETUGT: return "setcc:setugt"; case ISD::SETUGT: return "setcc:setugt";
@ -1608,7 +1608,7 @@ const char *SDNode::getOperationName() const {
case ISD::SETULT: return "setcc:setult"; case ISD::SETULT: return "setcc:setult";
case ISD::SETULE: return "setcc:setule"; case ISD::SETULE: return "setcc:setule";
case ISD::SETUNE: return "setcc:setune"; case ISD::SETUNE: return "setcc:setune";
case ISD::SETEQ: return "setcc:seteq"; case ISD::SETEQ: return "setcc:seteq";
case ISD::SETGT: return "setcc:setgt"; case ISD::SETGT: return "setcc:setgt";
case ISD::SETGE: return "setcc:setge"; case ISD::SETGE: return "setcc:setge";
@ -1643,7 +1643,7 @@ void SDNode::dump() const {
std::cerr << "<" << CSDN->getValue() << ">"; std::cerr << "<" << CSDN->getValue() << ">";
} else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
std::cerr << "<" << CSDN->getValue() << ">"; std::cerr << "<" << CSDN->getValue() << ">";
} else if (const GlobalAddressSDNode *GADN = } else if (const GlobalAddressSDNode *GADN =
dyn_cast<GlobalAddressSDNode>(this)) { dyn_cast<GlobalAddressSDNode>(this)) {
std::cerr << "<"; std::cerr << "<";
WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; WriteAsOperand(std::cerr, GADN->getGlobal()) << ">";
@ -1652,7 +1652,7 @@ void SDNode::dump() const {
std::cerr << "<" << FIDN->getIndex() << ">"; std::cerr << "<" << FIDN->getIndex() << ">";
} else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
std::cerr << "<" << CP->getIndex() << ">"; std::cerr << "<" << CP->getIndex() << ">";
} else if (const BasicBlockSDNode *BBDN = } else if (const BasicBlockSDNode *BBDN =
dyn_cast<BasicBlockSDNode>(this)) { dyn_cast<BasicBlockSDNode>(this)) {
std::cerr << "<"; std::cerr << "<";
const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
@ -1676,7 +1676,7 @@ static void DumpNodes(SDNode *N, unsigned indent) {
else else
std::cerr << "\n" << std::string(indent+2, ' ') std::cerr << "\n" << std::string(indent+2, ' ')
<< (void*)N->getOperand(i).Val << ": <multiple use>"; << (void*)N->getOperand(i).Val << ": <multiple use>";
std::cerr << "\n" << std::string(indent, ' '); std::cerr << "\n" << std::string(indent, ' ');
N->dump(); N->dump();

56
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1,10 +1,10 @@
//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This implements the SelectionDAGISel class. // This implements the SelectionDAGISel class.
@ -79,7 +79,7 @@ namespace llvm {
unsigned MakeReg(MVT::ValueType VT) { unsigned MakeReg(MVT::ValueType VT) {
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
} }
unsigned CreateRegForValue(const Value *V) { unsigned CreateRegForValue(const Value *V) {
MVT::ValueType VT = TLI.getValueType(V->getType()); MVT::ValueType VT = TLI.getValueType(V->getType());
// The common case is that we will only create one register for this // The common case is that we will only create one register for this
@ -89,19 +89,19 @@ namespace llvm {
// If we are promoting this value, pick the next largest supported type. // If we are promoting this value, pick the next largest supported type.
return MakeReg(TLI.getTypeToTransformTo(VT)); return MakeReg(TLI.getTypeToTransformTo(VT));
} }
// If this value is represented with multiple target registers, make sure // If this value is represented with multiple target registers, make sure
// to create enough consequtive registers of the right (smaller) type. // to create enough consequtive registers of the right (smaller) type.
unsigned NT = VT-1; // Find the type to use. unsigned NT = VT-1; // Find the type to use.
while (TLI.getNumElements((MVT::ValueType)NT) != 1) while (TLI.getNumElements((MVT::ValueType)NT) != 1)
--NT; --NT;
unsigned R = MakeReg((MVT::ValueType)NT); unsigned R = MakeReg((MVT::ValueType)NT);
for (unsigned i = 1; i != NV; ++i) for (unsigned i = 1; i != NV; ++i)
MakeReg((MVT::ValueType)NT); MakeReg((MVT::ValueType)NT);
return R; return R;
} }
unsigned InitializeRegForValue(const Value *V) { unsigned InitializeRegForValue(const Value *V) {
unsigned &R = ValueMap[V]; unsigned &R = ValueMap[V];
assert(R == 0 && "Already initialized this value register!"); assert(R == 0 && "Already initialized this value register!");
@ -122,7 +122,7 @@ static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
} }
FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
Function &fn, MachineFunction &mf) Function &fn, MachineFunction &mf)
: TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
// Initialize the mapping of values to registers. This is only set up for // Initialize the mapping of values to registers. This is only set up for
@ -206,7 +206,7 @@ public:
FunctionLoweringInfo &FuncInfo; FunctionLoweringInfo &FuncInfo;
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
FunctionLoweringInfo &funcinfo) FunctionLoweringInfo &funcinfo)
: TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
FuncInfo(funcinfo) { FuncInfo(funcinfo) {
} }
@ -216,7 +216,7 @@ public:
SDOperand getRoot() { SDOperand getRoot() {
if (PendingLoads.empty()) if (PendingLoads.empty())
return DAG.getRoot(); return DAG.getRoot();
if (PendingLoads.size() == 1) { if (PendingLoads.size() == 1) {
SDOperand Root = PendingLoads[0]; SDOperand Root = PendingLoads[0];
DAG.setRoot(Root); DAG.setRoot(Root);
@ -558,7 +558,7 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN); IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN);
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
} }
} }
@ -615,7 +615,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
void SelectionDAGLowering::visitLoad(LoadInst &I) { void SelectionDAGLowering::visitLoad(LoadInst &I) {
SDOperand Ptr = getValue(I.getOperand(0)); SDOperand Ptr = getValue(I.getOperand(0));
SDOperand Root; SDOperand Root;
if (I.isVolatile()) if (I.isVolatile())
Root = getRoot(); Root = getRoot();
@ -672,7 +672,7 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return; case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return;
case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return; case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return;
case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return; case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
case Intrinsic::isunordered: case Intrinsic::isunordered:
setValue(&I, DAG.getSetCC(ISD::SETUO, MVT::i1,getValue(I.getOperand(1)), setValue(&I, DAG.getSetCC(ISD::SETUO, MVT::i1,getValue(I.getOperand(1)),
getValue(I.getOperand(2)))); getValue(I.getOperand(2))));
@ -683,23 +683,23 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
return; return;
} }
} }
SDOperand Callee; SDOperand Callee;
if (!RenameFn) if (!RenameFn)
Callee = getValue(I.getOperand(0)); Callee = getValue(I.getOperand(0));
else else
Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
std::vector<std::pair<SDOperand, const Type*> > Args; std::vector<std::pair<SDOperand, const Type*> > Args;
for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
Value *Arg = I.getOperand(i); Value *Arg = I.getOperand(i);
SDOperand ArgNode = getValue(Arg); SDOperand ArgNode = getValue(Arg);
Args.push_back(std::make_pair(ArgNode, Arg->getType())); Args.push_back(std::make_pair(ArgNode, Arg->getType()));
} }
const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType()); const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
std::pair<SDOperand,SDOperand> Result = std::pair<SDOperand,SDOperand> Result =
TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), Callee, Args, DAG); TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), Callee, Args, DAG);
if (I.getType() != Type::VoidTy) if (I.getType() != Type::VoidTy)
@ -726,7 +726,7 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) {
Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType())); Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
std::pair<SDOperand,SDOperand> Result = std::pair<SDOperand,SDOperand> Result =
TLI.LowerCallTo(getRoot(), I.getType(), false, TLI.LowerCallTo(getRoot(), I.getType(), false,
DAG.getExternalSymbol("malloc", IntPtr), DAG.getExternalSymbol("malloc", IntPtr),
Args, DAG); Args, DAG);
setValue(&I, Result.first); // Pointers always fit in registers setValue(&I, Result.first); // Pointers always fit in registers
@ -784,7 +784,7 @@ void SelectionDAGLowering::visitVAStart(CallInst &I) {
void SelectionDAGLowering::visitVAArg(VAArgInst &I) { void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
std::pair<SDOperand,SDOperand> Result = std::pair<SDOperand,SDOperand> Result =
TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)), TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)),
I.getType(), DAG); I.getType(), DAG);
setValue(&I, Result.first); setValue(&I, Result.first);
DAG.setRoot(Result.second); DAG.setRoot(Result.second);
@ -792,7 +792,7 @@ void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
void SelectionDAGLowering::visitVANext(VANextInst &I) { void SelectionDAGLowering::visitVANext(VANextInst &I) {
std::pair<SDOperand,SDOperand> Result = std::pair<SDOperand,SDOperand> Result =
TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)), TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)),
I.getArgType(), DAG); I.getArgType(), DAG);
setValue(&I, Result.first); setValue(&I, Result.first);
DAG.setRoot(Result.second); DAG.setRoot(Result.second);
@ -861,7 +861,7 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
SelectBasicBlock(I, MF, FuncInfo); SelectBasicBlock(I, MF, FuncInfo);
return true; return true;
} }
@ -915,7 +915,7 @@ LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
AI != E; ++AI,++a) AI != E; ++AI,++a)
if (!AI->use_empty()) { if (!AI->use_empty()) {
SDL.setValue(AI, Args[a]); SDL.setValue(AI, Args[a]);
SDOperand Copy = SDOperand Copy =
CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]); CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
UnorderedChains.push_back(Copy); UnorderedChains.push_back(Copy);
} }
@ -931,7 +931,7 @@ LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
std::make_pair(AI, a))); std::make_pair(AI, a)));
} else { } else {
SDL.setValue(AI, Args[a]); SDL.setValue(AI, Args[a]);
SDOperand Copy = SDOperand Copy =
CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]); CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
UnorderedChains.push_back(Copy); UnorderedChains.push_back(Copy);
} }
@ -948,12 +948,12 @@ LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) { if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) {
// Lower the arguments into this block. // Lower the arguments into this block.
std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
// Set up the value mapping for the local arguments. // Set up the value mapping for the local arguments.
for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB; for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB;
++BLAI) ++BLAI)
SDL.setValue(BLAI->second.first, Args[BLAI->second.second]); SDL.setValue(BLAI->second.first, Args[BLAI->second.second]);
// Any dead arguments will just be ignored here. // Any dead arguments will just be ignored here.
} }
} }
@ -966,7 +966,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
SelectionDAGLowering SDL(DAG, TLI, FuncInfo); SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
std::vector<SDOperand> UnorderedChains; std::vector<SDOperand> UnorderedChains;
// Lower any arguments needed in this block. // Lower any arguments needed in this block.
LowerArguments(LLVMBB, SDL, UnorderedChains); LowerArguments(LLVMBB, SDL, UnorderedChains);
@ -994,7 +994,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
// directly add them, because expansion might result in multiple MBB's for one // directly add them, because expansion might result in multiple MBB's for one
// BB. As such, the start of the BB might correspond to a different MBB than // BB. As such, the start of the BB might correspond to a different MBB than
// the end. // the end.
// //
// Emit constants only once even if used by multiple PHI nodes. // Emit constants only once even if used by multiple PHI nodes.
std::map<Constant*, unsigned> ConstantsOut; std::map<Constant*, unsigned> ConstantsOut;
@ -1026,7 +1026,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
} else { } else {
Reg = FuncInfo.ValueMap[PHIOp]; Reg = FuncInfo.ValueMap[PHIOp];
if (Reg == 0) { if (Reg == 0) {
assert(isa<AllocaInst>(PHIOp) && assert(isa<AllocaInst>(PHIOp) &&
FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
"Didn't codegen value into a register!??"); "Didn't codegen value into a register!??");
Reg = FuncInfo.CreateRegForValue(PHIOp); Reg = FuncInfo.CreateRegForValue(PHIOp);
@ -1034,7 +1034,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
CopyValueToVirtualRegister(SDL, PHIOp, Reg)); CopyValueToVirtualRegister(SDL, PHIOp, Reg));
} }
} }
// Remember that this register needs to added to the machine PHI node as // Remember that this register needs to added to the machine PHI node as
// the input for this MBB. // the input for this MBB.
unsigned NumElements = unsigned NumElements =

10
lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
View File

@ -1,10 +1,10 @@
//===-- SelectionDAGPrinter.cpp - Implement SelectionDAG::viewGraph() -----===// //===-- SelectionDAGPrinter.cpp - Implement SelectionDAG::viewGraph() -----===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This implements the SelectionDAG::viewGraph method. // This implements the SelectionDAG::viewGraph method.
@ -70,7 +70,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
Op += ": " + utostr(CSDN->getValue()); Op += ": " + utostr(CSDN->getValue());
} else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(Node)) { } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(Node)) {
Op += ": " + ftostr(CSDN->getValue()); Op += ": " + ftostr(CSDN->getValue());
} else if (const GlobalAddressSDNode *GADN = } else if (const GlobalAddressSDNode *GADN =
dyn_cast<GlobalAddressSDNode>(Node)) { dyn_cast<GlobalAddressSDNode>(Node)) {
Op += ": " + GADN->getGlobal()->getName(); Op += ": " + GADN->getGlobal()->getName();
} else if (const FrameIndexSDNode *FIDN = } else if (const FrameIndexSDNode *FIDN =
@ -78,7 +78,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
Op += " " + itostr(FIDN->getIndex()); Op += " " + itostr(FIDN->getIndex());
} else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Node)){ } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Node)){
Op += "<" + utostr(CP->getIndex()) + ">"; Op += "<" + utostr(CP->getIndex()) + ">";
} else if (const BasicBlockSDNode *BBDN = } else if (const BasicBlockSDNode *BBDN =
dyn_cast<BasicBlockSDNode>(Node)) { dyn_cast<BasicBlockSDNode>(Node)) {
Op = "BB: "; Op = "BB: ";
const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
@ -95,7 +95,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
} }
return Op; return Op;
} }
/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
/// rendered using 'dot'. /// rendered using 'dot'.

8
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -57,7 +57,7 @@ namespace {
bool runOnMachineFunction(MachineFunction&); bool runOnMachineFunction(MachineFunction&);
}; };
RegisterPass<TwoAddressInstructionPass> RegisterPass<TwoAddressInstructionPass>
X("twoaddressinstruction", "Two-Address instruction pass"); X("twoaddressinstruction", "Two-Address instruction pass");
}; };
@ -152,7 +152,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
mbbi->insert(mi, NewMI); // Insert the new inst mbbi->insert(mi, NewMI); // Insert the new inst
mbbi->erase(mi); // Nuke the old inst. mbbi->erase(mi); // Nuke the old inst.
mi = NewMI; mi = NewMI;
} }
++NumCommuted; ++NumCommuted;
regB = regC; regB = regC;
@ -161,7 +161,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
} }
} }
// If this instruction is potentially convertible to a true // If this instruction is potentially convertible to a true
// three-address instruction, // three-address instruction,
if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR) if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
if (MachineInstr *New = TII.convertToThreeAddress(mi)) { if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi); DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
@ -197,7 +197,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
// replace all occurences of regB with regA // replace all occurences of regB with regA
for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) { for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
if (mi->getOperand(i).isRegister() && if (mi->getOperand(i).isRegister() &&
mi->getOperand(i).getReg() == regB) mi->getOperand(i).getReg() == regB)
mi->SetMachineOperandReg(i, regA); mi->SetMachineOperandReg(i, regA);
} }

6
lib/CodeGen/UnreachableBlockElim.cpp
View File

@ -1,12 +1,12 @@
//===-- UnreachableBlockElim.cpp - Remove unreachable blocks for codegen --===// //===-- UnreachableBlockElim.cpp - Remove unreachable blocks for codegen --===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This pass is an extremely simple version of the SimplifyCFG pass. Its sole // This pass is an extremely simple version of the SimplifyCFG pass. Its sole
// job is to delete LLVM basic blocks that are not reachable from the entry // job is to delete LLVM basic blocks that are not reachable from the entry
// node. To do this, it performs a simple depth first traversal of the CFG, // node. To do this, it performs a simple depth first traversal of the CFG,

4
lib/CodeGen/ValueTypes.cpp
View File

@ -1,10 +1,10 @@
//===-- ValueTypes.cpp - Implementation of MVT::ValueType methods ---------===// //===-- ValueTypes.cpp - Implementation of MVT::ValueType methods ---------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements methods in the CodeGen/ValueTypes.h header. // This file implements methods in the CodeGen/ValueTypes.h header.

22
lib/CodeGen/VirtRegMap.cpp
View File

@ -82,7 +82,7 @@ void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
unsigned OpNo, MachineInstr *NewMI) { unsigned OpNo, MachineInstr *NewMI) {
// Move previous memory references folded to new instruction. // Move previous memory references folded to new instruction.
MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
MI2VirtMap.erase(I++); MI2VirtMap.erase(I++);
@ -108,7 +108,7 @@ void VirtRegMap::print(std::ostream &OS) const {
e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
} }
for (unsigned i = MRegisterInfo::FirstVirtualRegister, for (unsigned i = MRegisterInfo::FirstVirtualRegister,
@ -163,7 +163,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF,
unsigned PhysReg = VRM.getPhys(VirtReg); unsigned PhysReg = VRM.getPhys(VirtReg);
if (VRM.hasStackSlot(VirtReg)) { if (VRM.hasStackSlot(VirtReg)) {
int StackSlot = VRM.getStackSlot(VirtReg); int StackSlot = VRM.getStackSlot(VirtReg);
if (MO.isUse() && if (MO.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
== LoadedRegs.end()) { == LoadedRegs.end()) {
@ -172,7 +172,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF,
++NumLoads; ++NumLoads;
DEBUG(std::cerr << '\t' << *prior(MII)); DEBUG(std::cerr << '\t' << *prior(MII));
} }
if (MO.isDef()) { if (MO.isDef()) {
MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot); MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
++NumStores; ++NumStores;
@ -255,16 +255,16 @@ namespace {
struct ReusedOp { struct ReusedOp {
// The MachineInstr operand that reused an available value. // The MachineInstr operand that reused an available value.
unsigned Operand; unsigned Operand;
// StackSlot - The spill slot of the value being reused. // StackSlot - The spill slot of the value being reused.
unsigned StackSlot; unsigned StackSlot;
// PhysRegReused - The physical register the value was available in. // PhysRegReused - The physical register the value was available in.
unsigned PhysRegReused; unsigned PhysRegReused;
// AssignedPhysReg - The physreg that was assigned for use by the reload. // AssignedPhysReg - The physreg that was assigned for use by the reload.
unsigned AssignedPhysReg; unsigned AssignedPhysReg;
ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr) ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr)
: Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr) {} : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr) {}
}; };
@ -384,7 +384,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
// Okay, we found out that an alias of a reused register // Okay, we found out that an alias of a reused register
// was used. This isn't good because it means we have // was used. This isn't good because it means we have
// to undo a previous reuse. // to undo a previous reuse.
MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg, MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
Op.StackSlot); Op.StackSlot);
ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable, ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
PhysRegsAvailable); PhysRegsAvailable);
@ -510,12 +510,12 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
break; break;
} }
} }
if (!OpTakenCareOf) { if (!OpTakenCareOf) {
ClobberPhysReg(VirtReg, SpillSlotsAvailable, PhysRegsAvailable); ClobberPhysReg(VirtReg, SpillSlotsAvailable, PhysRegsAvailable);
TakenCareOf = true; TakenCareOf = true;
} }
} }
if (!TakenCareOf) { if (!TakenCareOf) {
// The only vregs left are stack slot definitions. // The only vregs left are stack slot definitions.

2
lib/CodeGen/VirtRegMap.h
View File

@ -48,7 +48,7 @@ namespace llvm {
/// instructions, we need to know which virtual register was /// instructions, we need to know which virtual register was
/// read/written by this instruction. /// read/written by this instruction.
MI2VirtMapTy MI2VirtMap; MI2VirtMapTy MI2VirtMap;
VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT
void operator=(const VirtRegMap&); // DO NOT IMPLEMENT void operator=(const VirtRegMap&); // DO NOT IMPLEMENT

12
lib/Debugger/Debugger.cpp
View File

@ -1,12 +1,12 @@
//===-- Debugger.cpp - LLVM debugger library implementation ---------------===// //===-- Debugger.cpp - LLVM debugger library implementation ---------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file contains the main implementation of the LLVM debugger library. // This file contains the main implementation of the LLVM debugger library.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -32,7 +32,7 @@ Debugger::~Debugger() {
} catch (const char *) { } catch (const char *) {
} catch (const std::string &) { } catch (const std::string &) {
} }
unloadProgram(); unloadProgram();
} }
@ -47,7 +47,7 @@ getMaterializedModuleProvider(const std::string &Filename) {
try { try {
std::auto_ptr<ModuleProvider> Result(getBytecodeModuleProvider(Filename)); std::auto_ptr<ModuleProvider> Result(getBytecodeModuleProvider(Filename));
if (!Result.get()) return 0; if (!Result.get()) return 0;
Result->materializeModule(); Result->materializeModule();
return Result.release()->releaseModule(); return Result.release()->releaseModule();
} catch (...) { } catch (...) {
@ -163,7 +163,7 @@ void Debugger::nextProgram() {
// Don't trust the current frame: get the caller frame. // Don't trust the current frame: get the caller frame.
void *ParentFrame = Process->getPreviousFrame(CurrentFrame); void *ParentFrame = Process->getPreviousFrame(CurrentFrame);
// Ok, we have some information, run the program one step. // Ok, we have some information, run the program one step.
Process->stepProgram(); Process->stepProgram();

8
lib/Debugger/FDHandle.cpp
View File

@ -1,10 +1,10 @@
//===- lib/Debugger/FDHandle.cpp - File Descriptor Handle -----------------===// //===- lib/Debugger/FDHandle.cpp - File Descriptor Handle -----------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements a class for ensuring that Unix file handles get closed. // This file implements a class for ensuring that Unix file handles get closed.
@ -21,12 +21,12 @@ using namespace llvm;
// //
FDHandle::~FDHandle() throw() { FDHandle::~FDHandle() throw() {
if (FD != -1) if (FD != -1)
::close(FD); ::close(FD);
} }
FDHandle &FDHandle::operator=(int fd) throw() { FDHandle &FDHandle::operator=(int fd) throw() {
if (FD != -1) if (FD != -1)
::close(FD); ::close(FD);
FD = fd; FD = fd;
return *this; return *this;

4
lib/Debugger/FDHandle.h
View File

@ -1,10 +1,10 @@
//===- lib/Debugger/FDHandle.h - File Descriptor Handle ---------*- C++ -*-===// //===- lib/Debugger/FDHandle.h - File Descriptor Handle ---------*- C++ -*-===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file defines a family of utility functions which are useful for doing // This file defines a family of utility functions which are useful for doing

20
lib/Debugger/ProgramInfo.cpp
View File

@ -1,12 +1,12 @@
//===-- ProgramInfo.cpp - Compute and cache info about a program ----------===// //===-- ProgramInfo.cpp - Compute and cache info about a program ----------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the ProgramInfo and related classes, by sorting through // This file implements the ProgramInfo and related classes, by sorting through
// the loaded Module. // the loaded Module.
// //
@ -107,13 +107,13 @@ static const GlobalVariable *getNextStopPoint(const Value *V, unsigned &LineNo,
if (const ConstantInt *C = dyn_cast<ConstantInt>(CI->getOperand(3))) if (const ConstantInt *C = dyn_cast<ConstantInt>(CI->getOperand(3)))
CurColNo = C->getRawValue(); CurColNo = C->getRawValue();
const Value *Op = CI->getOperand(4); const Value *Op = CI->getOperand(4);
if ((CurDesc = dyn_cast<GlobalVariable>(Op)) && if ((CurDesc = dyn_cast<GlobalVariable>(Op)) &&
(LineNo < LastLineNo || (LineNo < LastLineNo ||
(LineNo == LastLineNo && ColNo < LastColNo))) { (LineNo == LastLineNo && ColNo < LastColNo))) {
LastDesc = CurDesc; LastDesc = CurDesc;
LastLineNo = CurLineNo; LastLineNo = CurLineNo;
LastColNo = CurColNo; LastColNo = CurColNo;
} }
ShouldRecurse = false; ShouldRecurse = false;
} }
@ -128,12 +128,12 @@ static const GlobalVariable *getNextStopPoint(const Value *V, unsigned &LineNo,
if (LineNo < LastLineNo || (LineNo == LastLineNo && ColNo < LastColNo)){ if (LineNo < LastLineNo || (LineNo == LastLineNo && ColNo < LastColNo)){
LastDesc = GV; LastDesc = GV;
LastLineNo = CurLineNo; LastLineNo = CurLineNo;
LastColNo = CurColNo; LastColNo = CurColNo;
} }
} }
} }
} }
if (LastDesc) { if (LastDesc) {
LineNo = LastLineNo != ~0U ? LastLineNo : 0; LineNo = LastLineNo != ~0U ? LastLineNo : 0;
ColNo = LastColNo != ~0U ? LastColNo : 0; ColNo = LastColNo != ~0U ? LastColNo : 0;
@ -157,7 +157,7 @@ SourceFileInfo::SourceFileInfo(const GlobalVariable *Desc,
if (CS->getNumOperands() > 4) { if (CS->getNumOperands() > 4) {
if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(CS->getOperand(1))) if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(CS->getOperand(1)))
Version = CUI->getValue(); Version = CUI->getValue();
BaseName = getStringValue(CS->getOperand(3)); BaseName = getStringValue(CS->getOperand(3));
Directory = getStringValue(CS->getOperand(4)); Directory = getStringValue(CS->getOperand(4));
} }
@ -194,7 +194,7 @@ SourceFunctionInfo::SourceFunctionInfo(ProgramInfo &PI,
if (ConstantStruct *CS = dyn_cast<ConstantStruct>(Desc->getInitializer())) if (ConstantStruct *CS = dyn_cast<ConstantStruct>(Desc->getInitializer()))
if (CS->getNumOperands() > 2) { if (CS->getNumOperands() > 2) {
// Entry #1 is the file descriptor. // Entry #1 is the file descriptor.
if (const GlobalVariable *GV = if (const GlobalVariable *GV =
dyn_cast<GlobalVariable>(CS->getOperand(1))) dyn_cast<GlobalVariable>(CS->getOperand(1)))
SourceFile = &PI.getSourceFile(GV); SourceFile = &PI.getSourceFile(GV);
@ -338,7 +338,7 @@ const SourceFileInfo &ProgramInfo::getSourceFile(const std::string &Filename) {
std::multimap<std::string, SourceFileInfo*>::const_iterator Start, End; std::multimap<std::string, SourceFileInfo*>::const_iterator Start, End;
getSourceFiles(); getSourceFiles();
tie(Start, End) = SourceFileIndex.equal_range(Filename); tie(Start, End) = SourceFileIndex.equal_range(Filename);
if (Start == End) throw "Could not find source file '" + Filename + "'!"; if (Start == End) throw "Could not find source file '" + Filename + "'!";
const SourceFileInfo &SFI = *Start->second; const SourceFileInfo &SFI = *Start->second;
++Start; ++Start;

8
lib/Debugger/RuntimeInfo.cpp
View File

@ -1,12 +1,12 @@
//===-- RuntimeInfo.cpp - Compute and cache info about running program ----===// //===-- RuntimeInfo.cpp - Compute and cache info about running program ----===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the RuntimeInfo and related classes, by querying and // This file implements the RuntimeInfo and related classes, by querying and
// cachine information from the running inferior process. // cachine information from the running inferior process.
// //
@ -24,7 +24,7 @@ StackFrame::StackFrame(RuntimeInfo &ri, void *ParentFrameID)
: RI(ri), SourceInfo(0) { : RI(ri), SourceInfo(0) {
FrameID = RI.getInferiorProcess().getPreviousFrame(ParentFrameID); FrameID = RI.getInferiorProcess().getPreviousFrame(ParentFrameID);
if (FrameID == 0) throw "Stack frame does not exist!"; if (FrameID == 0) throw "Stack frame does not exist!";
// Compute lazily as needed. // Compute lazily as needed.
FunctionDesc = 0; FunctionDesc = 0;
} }

8
lib/Debugger/SourceFile.cpp
View File

@ -1,12 +1,12 @@
//===-- SourceFile.cpp - SourceFile implementation for the debugger -------===// //===-- SourceFile.cpp - SourceFile implementation for the debugger -------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the SourceFile class for the LLVM debugger. // This file implements the SourceFile class for the LLVM debugger.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -16,7 +16,7 @@
using namespace llvm; using namespace llvm;
/// readFile - Load Filename /// readFile - Load Filename
/// ///
void SourceFile::readFile() { void SourceFile::readFile() {
File.map(); File.map();

6
lib/Debugger/SourceLanguage-CFamily.cpp
View File

@ -1,12 +1,12 @@
//===-- SourceLanguage-CFamily.cpp - C family SourceLanguage impl ---------===// //===-- SourceLanguage-CFamily.cpp - C family SourceLanguage impl ---------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the SourceLanguage class for the C family of languages // This file implements the SourceLanguage class for the C family of languages
// (K&R C, C89, C99, etc). // (K&R C, C89, C99, etc).
// //

6
lib/Debugger/SourceLanguage-CPlusPlus.cpp
View File

@ -1,12 +1,12 @@
//===-- SourceLanguage-CPlusPlus.cpp - C++ SourceLanguage impl ------------===// //===-- SourceLanguage-CPlusPlus.cpp - C++ SourceLanguage impl ------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the SourceLanguage class for the C++ language. // This file implements the SourceLanguage class for the C++ language.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

6
lib/Debugger/SourceLanguage-Unknown.cpp
View File

@ -1,12 +1,12 @@
//===-- SourceLanguage-Unknown.cpp - Implement itf for unknown languages --===// //===-- SourceLanguage-Unknown.cpp - Implement itf for unknown languages --===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// If the LLVM debugger does not have a module for a particular language, it // If the LLVM debugger does not have a module for a particular language, it
// falls back on using this one to perform the source-language interface. This // falls back on using this one to perform the source-language interface. This
// interface is not wonderful, but it gets the job done. // interface is not wonderful, but it gets the job done.

6
lib/Debugger/SourceLanguage.cpp
View File

@ -1,12 +1,12 @@
//===-- SourceLanguage.cpp - Implement the SourceLanguage class -----------===// //===-- SourceLanguage.cpp - Implement the SourceLanguage class -----------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the SourceLanguage class. // This file implements the SourceLanguage class.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

18
lib/Debugger/UnixLocalInferiorProcess.cpp
View File

@ -1,12 +1,12 @@
//===-- UnixLocalInferiorProcess.cpp - A Local process on a Unixy system --===// //===-- UnixLocalInferiorProcess.cpp - A Local process on a Unixy system --===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file provides one implementation of the InferiorProcess class, which is // This file provides one implementation of the InferiorProcess class, which is
// designed to be used on unixy systems (those that support pipe, fork, exec, // designed to be used on unixy systems (those that support pipe, fork, exec,
// and signals). // and signals).
@ -94,7 +94,7 @@ namespace {
// FinishProgram: FrameDesc*->char - This command causes the program to // FinishProgram: FrameDesc*->char - This command causes the program to
// continue execution until the specified function frame returns. // continue execution until the specified function frame returns.
FinishProgram, FinishProgram,
// ContProgram: void->char - This command causes the program to continue // ContProgram: void->char - This command causes the program to continue
// execution, stopping at some point in the future. // execution, stopping at some point in the future.
@ -217,7 +217,7 @@ IP::IP(Module *M, const std::vector<std::string> &Arguments,
// Start the child running... // Start the child running...
startChild(M, Arguments, envp); startChild(M, Arguments, envp);
// Okay, we created the program and it is off and running. Wait for it to // Okay, we created the program and it is off and running. Wait for it to
// stop now. // stop now.
try { try {
@ -325,7 +325,7 @@ const GlobalVariable *IP::getSubprogramDesc(void *Frame) const {
/// getFrameLocation - This method returns the source location where each stack /// getFrameLocation - This method returns the source location where each stack
/// frame is stopped. /// frame is stopped.
void IP::getFrameLocation(void *Frame, unsigned &LineNo, unsigned &ColNo, void IP::getFrameLocation(void *Frame, unsigned &LineNo, unsigned &ColNo,
const GlobalVariable *&SourceDesc) const { const GlobalVariable *&SourceDesc) const {
sendCommand(GetFrameLocation, &Frame, sizeof(Frame)); sendCommand(GetFrameLocation, &Frame, sizeof(Frame));
LocationToken Loc; LocationToken Loc;
@ -419,7 +419,7 @@ void IP::writeToChild(void *Buffer, unsigned Size) const {
/// died, otherwise it just returns the exit code if it had to be killed. /// died, otherwise it just returns the exit code if it had to be killed.
void IP::killChild() const { void IP::killChild() const {
assert(ChildPID != 0 && "Child has already been reaped!"); assert(ChildPID != 0 && "Child has already been reaped!");
// If the process terminated on its own accord, closing the pipe file // If the process terminated on its own accord, closing the pipe file
// descriptors, we will get here. Check to see if the process has already // descriptors, we will get here. Check to see if the process has already
// died in this manner, gracefully. // died in this manner, gracefully.
@ -456,7 +456,7 @@ void IP::killChild() const {
throw InferiorProcessDead(WTERMSIG(Status)); throw InferiorProcessDead(WTERMSIG(Status));
throw InferiorProcessDead(-1); throw InferiorProcessDead(-1);
} }
// Otherwise, the child exists and has not yet been killed. // Otherwise, the child exists and has not yet been killed.
if (kill(ChildPID, SIGKILL) < 0) if (kill(ChildPID, SIGKILL) < 0)
throw "Error killing child process!"; throw "Error killing child process!";
@ -905,7 +905,7 @@ static void runChild(Module *M, const std::vector<std::string> &Arguments,
ExecutionEngine::create(new ExistingModuleProvider(M), false, ExecutionEngine::create(new ExistingModuleProvider(M), false,
new DebuggerIntrinsicLowering()); new DebuggerIntrinsicLowering());
assert(EE && "Couldn't create an ExecutionEngine, not even an interpreter?"); assert(EE && "Couldn't create an ExecutionEngine, not even an interpreter?");
// Call the main function from M as if its signature were: // Call the main function from M as if its signature were:
// int main (int argc, char **argv, const char **envp) // int main (int argc, char **argv, const char **envp)
// using the contents of Args to determine argc & argv, and the contents of // using the contents of Args to determine argc & argv, and the contents of

42
lib/ExecutionEngine/ExecutionEngine.cpp
View File

@ -1,12 +1,12 @@
//===-- ExecutionEngine.cpp - Common Implementation shared by EEs ---------===// //===-- ExecutionEngine.cpp - Common Implementation shared by EEs ---------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details. // the University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file defines the common interface used by the various execution engine // This file defines the common interface used by the various execution engine
// subclasses. // subclasses.
// //
@ -33,7 +33,7 @@ namespace {
Statistic<> NumGlobals ("lli", "Number of global vars initialized"); Statistic<> NumGlobals ("lli", "Number of global vars initialized");
} }
ExecutionEngine::ExecutionEngine(ModuleProvider *P) : ExecutionEngine::ExecutionEngine(ModuleProvider *P) :
CurMod(*P->getModule()), MP(P) { CurMod(*P->getModule()), MP(P) {
assert(P && "ModuleProvider is null?"); assert(P && "ModuleProvider is null?");
} }
@ -52,7 +52,7 @@ ExecutionEngine::~ExecutionEngine() {
const GlobalValue *ExecutionEngine::getGlobalValueAtAddress(void *Addr) { const GlobalValue *ExecutionEngine::getGlobalValueAtAddress(void *Addr) {
// If we haven't computed the reverse mapping yet, do so first. // If we haven't computed the reverse mapping yet, do so first.
if (GlobalAddressReverseMap.empty()) { if (GlobalAddressReverseMap.empty()) {
for (std::map<const GlobalValue*, void *>::iterator I = for (std::map<const GlobalValue*, void *>::iterator I =
GlobalAddressMap.begin(), E = GlobalAddressMap.end(); I != E; ++I) GlobalAddressMap.begin(), E = GlobalAddressMap.end(); I != E; ++I)
GlobalAddressReverseMap.insert(std::make_pair(I->second, I->first)); GlobalAddressReverseMap.insert(std::make_pair(I->second, I->first));
} }
@ -77,10 +77,10 @@ static void *CreateArgv(ExecutionEngine *EE,
unsigned Size = InputArgv[i].size()+1; unsigned Size = InputArgv[i].size()+1;
char *Dest = new char[Size]; char *Dest = new char[Size];
DEBUG(std::cerr << "ARGV[" << i << "] = " << (void*)Dest << "\n"); DEBUG(std::cerr << "ARGV[" << i << "] = " << (void*)Dest << "\n");
std::copy(InputArgv[i].begin(), InputArgv[i].end(), Dest); std::copy(InputArgv[i].begin(), InputArgv[i].end(), Dest);
Dest[Size-1] = 0; Dest[Size-1] = 0;
// Endian safe: Result[i] = (PointerTy)Dest; // Endian safe: Result[i] = (PointerTy)Dest;
EE->StoreValueToMemory(PTOGV(Dest), (GenericValue*)(Result+i*PtrSize), EE->StoreValueToMemory(PTOGV(Dest), (GenericValue*)(Result+i*PtrSize),
SBytePtr); SBytePtr);
@ -124,9 +124,9 @@ int ExecutionEngine::runFunctionAsMain(Function *Fn,
/// If possible, create a JIT, unless the caller specifically requests an /// If possible, create a JIT, unless the caller specifically requests an
/// Interpreter or there's an error. If even an Interpreter cannot be created, /// Interpreter or there's an error. If even an Interpreter cannot be created,
/// NULL is returned. /// NULL is returned.
/// ///
ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP, ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
bool ForceInterpreter, bool ForceInterpreter,
IntrinsicLowering *IL) { IntrinsicLowering *IL) {
ExecutionEngine *EE = 0; ExecutionEngine *EE = 0;
@ -151,10 +151,10 @@ ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
} }
} }
if (EE == 0) if (EE == 0)
delete IL; delete IL;
else else
// Make sure we can resolve symbols in the program as well. The zero arg // Make sure we can resolve symbols in the program as well. The zero arg
// to the function tells DynamicLibrary to load the program, not a library. // to the function tells DynamicLibrary to load the program, not a library.
sys::DynamicLibrary::LoadLibraryPermanently(0); sys::DynamicLibrary::LoadLibraryPermanently(0);
@ -173,7 +173,7 @@ void *ExecutionEngine::getPointerToGlobal(const GlobalValue *GV) {
} }
/// FIXME: document /// FIXME: document
/// ///
GenericValue ExecutionEngine::getConstantValue(const Constant *C) { GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
GenericValue Result; GenericValue Result;
if (isa<UndefValue>(C)) return Result; if (isa<UndefValue>(C)) return Result;
@ -185,7 +185,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
std::vector<Value*> Indexes(CE->op_begin()+1, CE->op_end()); std::vector<Value*> Indexes(CE->op_begin()+1, CE->op_end());
uint64_t Offset = uint64_t Offset =
TD->getIndexedOffset(CE->getOperand(0)->getType(), Indexes); TD->getIndexedOffset(CE->getOperand(0)->getType(), Indexes);
Result.LongVal += Offset; Result.LongVal += Offset;
return Result; return Result;
} }
@ -203,7 +203,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
// Handle a cast of pointer to any integral type... // Handle a cast of pointer to any integral type...
if (isa<PointerType>(Op->getType()) && C->getType()->isIntegral()) if (isa<PointerType>(Op->getType()) && C->getType()->isIntegral())
return GV; return GV;
// Handle cast of integer to a pointer... // Handle cast of integer to a pointer...
if (isa<PointerType>(C->getType()) && Op->getType()->isIntegral()) if (isa<PointerType>(C->getType()) && Op->getType()->isIntegral())
switch (Op->getType()->getTypeID()) { switch (Op->getType()->getTypeID()) {
@ -260,7 +260,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
std::cerr << "ConstantExpr not handled as global var init: " << *CE << "\n"; std::cerr << "ConstantExpr not handled as global var init: " << *CE << "\n";
abort(); abort();
} }
switch (C->getType()->getTypeID()) { switch (C->getType()->getTypeID()) {
#define GET_CONST_VAL(TY, CTY, CLASS) \ #define GET_CONST_VAL(TY, CTY, CLASS) \
case Type::TY##TyID: Result.TY##Val = (CTY)cast<CLASS>(C)->getValue(); break case Type::TY##TyID: Result.TY##Val = (CTY)cast<CLASS>(C)->getValue(); break
@ -353,7 +353,7 @@ void ExecutionEngine::StoreValueToMemory(GenericValue Val, GenericValue *Ptr,
case Type::DoubleTyID: case Type::DoubleTyID:
case Type::ULongTyID: case Type::ULongTyID:
case Type::LongTyID: case Type::LongTyID:
Ptr->Untyped[7] = (unsigned char)(Val.ULongVal ); Ptr->Untyped[7] = (unsigned char)(Val.ULongVal );
Ptr->Untyped[6] = (unsigned char)(Val.ULongVal >> 8); Ptr->Untyped[6] = (unsigned char)(Val.ULongVal >> 8);
Ptr->Untyped[5] = (unsigned char)(Val.ULongVal >> 16); Ptr->Untyped[5] = (unsigned char)(Val.ULongVal >> 16);
Ptr->Untyped[4] = (unsigned char)(Val.ULongVal >> 24); Ptr->Untyped[4] = (unsigned char)(Val.ULongVal >> 24);
@ -382,7 +382,7 @@ GenericValue ExecutionEngine::LoadValueFromMemory(GenericValue *Ptr,
case Type::ShortTyID: Result.UShortVal = (unsigned)Ptr->Untyped[0] | case Type::ShortTyID: Result.UShortVal = (unsigned)Ptr->Untyped[0] |
((unsigned)Ptr->Untyped[1] << 8); ((unsigned)Ptr->Untyped[1] << 8);
break; break;
Load4BytesLittleEndian: Load4BytesLittleEndian:
case Type::FloatTyID: case Type::FloatTyID:
case Type::UIntTyID: case Type::UIntTyID:
case Type::IntTyID: Result.UIntVal = (unsigned)Ptr->Untyped[0] | case Type::IntTyID: Result.UIntVal = (unsigned)Ptr->Untyped[0] |
@ -463,7 +463,7 @@ void ExecutionEngine::InitializeMemory(const Constant *Init, void *Addr) {
switch (Init->getType()->getTypeID()) { switch (Init->getType()->getTypeID()) {
case Type::ArrayTyID: { case Type::ArrayTyID: {
const ConstantArray *CPA = cast<ConstantArray>(Init); const ConstantArray *CPA = cast<ConstantArray>(Init);
unsigned ElementSize = unsigned ElementSize =
getTargetData().getTypeSize(cast<ArrayType>(CPA->getType())->getElementType()); getTargetData().getTypeSize(cast<ArrayType>(CPA->getType())->getElementType());
for (unsigned i = 0, e = CPA->getNumOperands(); i != e; ++i) for (unsigned i = 0, e = CPA->getNumOperands(); i != e; ++i)
InitializeMemory(CPA->getOperand(i), (char*)Addr+i*ElementSize); InitializeMemory(CPA->getOperand(i), (char*)Addr+i*ElementSize);
@ -491,7 +491,7 @@ void ExecutionEngine::InitializeMemory(const Constant *Init, void *Addr) {
/// ///
void ExecutionEngine::emitGlobals() { void ExecutionEngine::emitGlobals() {
const TargetData &TD = getTargetData(); const TargetData &TD = getTargetData();
// Loop over all of the global variables in the program, allocating the memory // Loop over all of the global variables in the program, allocating the memory
// to hold them. // to hold them.
for (Module::const_global_iterator I = getModule().global_begin(), E = getModule().global_end(); for (Module::const_global_iterator I = getModule().global_begin(), E = getModule().global_end();
@ -499,7 +499,7 @@ void ExecutionEngine::emitGlobals() {
if (!I->isExternal()) { if (!I->isExternal()) {
// Get the type of the global... // Get the type of the global...
const Type *Ty = I->getType()->getElementType(); const Type *Ty = I->getType()->getElementType();
// Allocate some memory for it! // Allocate some memory for it!
unsigned Size = TD.getTypeSize(Ty); unsigned Size = TD.getTypeSize(Ty);
addGlobalMapping(I, new char[Size]); addGlobalMapping(I, new char[Size]);
@ -515,7 +515,7 @@ void ExecutionEngine::emitGlobals() {
abort(); abort();
} }
} }
// Now that all of the globals are set up in memory, loop through them all and // Now that all of the globals are set up in memory, loop through them all and
// initialize their contents. // initialize their contents.
for (Module::const_global_iterator I = getModule().global_begin(), E = getModule().global_end(); for (Module::const_global_iterator I = getModule().global_begin(), E = getModule().global_end();