From 775dd2a2a2031404be3be2f81d9f0cf6dfc5546b Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Wed, 22 Jul 2020 14:41:06 +0100 Subject: [PATCH] [AMDGPU] Set the default globals address space to 1 This will ensure that passes that add new global variables will create them in address space 1 once the passes have been updated to no longer default to the implicit address space zero. This also changes AutoUpgrade.cpp to add -G1 to the DataLayout if it wasn't already to present to ensure bitcode backwards compatibility. Reviewed by: arsenm Differential Revision: https://reviews.llvm.org/D84345 --- lib/Frontend/OpenMP/OMPIRBuilder.cpp | 2 +- lib/IR/AutoUpgrade.cpp | 10 ++++++++-- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 8 ++++---- unittests/Bitcode/DataLayoutUpgradeTest.cpp | 15 +++++++++++++++ 4 files changed, 28 insertions(+), 7 deletions(-) diff --git a/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/lib/Frontend/OpenMP/OMPIRBuilder.cpp index 6dfe26c36d7..0b676cda36f 100644 --- a/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -215,7 +215,7 @@ Value *OpenMPIRBuilder::getOrCreateIdent(Constant *SrcLocStr, GV->setAlignment(Align(8)); Ident = GV; } - return Ident; + return Builder.CreatePointerCast(Ident, IdentPtr); } Type *OpenMPIRBuilder::getLanemaskType() { diff --git a/lib/IR/AutoUpgrade.cpp b/lib/IR/AutoUpgrade.cpp index f5b235a5786..6d92f8cffee 100644 --- a/lib/IR/AutoUpgrade.cpp +++ b/lib/IR/AutoUpgrade.cpp @@ -4380,11 +4380,17 @@ MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { } std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) { - StringRef AddrSpaces = "-p270:32:32-p271:32:32-p272:64:64"; + Triple T(TT); + // For AMDGPU we uprgrade older DataLayouts to include the default globals + // address space of 1. + if (T.isAMDGPU() && !DL.contains("-G") && !DL.startswith("G")) { + return DL.empty() ? std::string("G1") : (DL + "-G1").str(); + } + std::string AddrSpaces = "-p270:32:32-p271:32:32-p272:64:64"; // If X86, and the datalayout matches the expected format, add pointer size // address spaces to the datalayout. - if (!Triple(TT).isX86() || DL.contains(AddrSpaces)) + if (!T.isX86() || DL.contains(AddrSpaces)) return std::string(DL); SmallVector Groups; diff --git a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index d97d6eaaa2a..ccfd62ea3e0 100644 --- a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -342,15 +342,15 @@ GCNILPSchedRegistry("gcn-ilp", static StringRef computeDataLayout(const Triple &TT) { if (TT.getArch() == Triple::r600) { // 32-bit pointers. - return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" - "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"; + return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" + "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"; } // 32-bit private, local, and region pointers. 64-bit global, constant and // flat, non-integral buffer fat pointers. - return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32" + return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" - "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" + "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1" "-ni:7"; } diff --git a/unittests/Bitcode/DataLayoutUpgradeTest.cpp b/unittests/Bitcode/DataLayoutUpgradeTest.cpp index c92418136e5..ec900471a83 100644 --- a/unittests/Bitcode/DataLayoutUpgradeTest.cpp +++ b/unittests/Bitcode/DataLayoutUpgradeTest.cpp @@ -27,6 +27,10 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) { "-f80:32-n8:16:32-S32"); EXPECT_EQ(DL3, "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128" "-n32:64-S128"); + + // Check that AMDGPU targets add -G1 if it's not present. + EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "r600"), "e-p:32:32-G1"); + EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64", "amdgcn"), "e-p:64:64-G1"); } TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) { @@ -46,6 +50,13 @@ TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) { EXPECT_EQ(DL2, "e-p:32:32"); EXPECT_EQ(DL3, "e-m:e-i64:64-n32:64"); EXPECT_EQ(DL4, "e-m:o-i64:64-i128:128-n32:64-S128"); + + // Check that AMDGPU targets don't add -G1 if there is already a -G flag. + EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32-G2", "r600"), "e-p:32:32-G2"); + EXPECT_EQ(UpgradeDataLayoutString("G2", "r600"), "G2"); + EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G2", "amdgcn"), "e-p:64:64-G2"); + EXPECT_EQ(UpgradeDataLayoutString("G2-e-p:64:64", "amdgcn"), "G2-e-p:64:64"); + EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G0", "amdgcn"), "e-p:64:64-G0"); } TEST(DataLayoutUpgradeTest, EmptyDataLayout) { @@ -54,6 +65,10 @@ TEST(DataLayoutUpgradeTest, EmptyDataLayout) { "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128", ""); EXPECT_EQ(DL1, ""); EXPECT_EQ(DL2, "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"); + + // Check that AMDGPU targets add G1 if it's not present. + EXPECT_EQ(UpgradeDataLayoutString("", "r600"), "G1"); + EXPECT_EQ(UpgradeDataLayoutString("", "amdgcn"), "G1"); } } // end namespace