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CodeGen: Change MachineInstr to use MachineInstr&, NFC

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Change MachineInstr API to prefer MachineInstr& over MachineInstr*
whenever the parameter is expected to be non-null.  Slowly inching
toward being able to fix PR26753.

llvm-svn: 262149
This commit is contained in:
Duncan P. N. Exon Smith 2016-02-27 20:01:33 +00:00
parent 71c5d5fa5f
commit 779625a4a6
14 changed files with 36 additions and 36 deletions
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6
include/llvm/CodeGen/MachineInstr.h
View File

@ -742,7 +742,7 @@ public:
/// Return true if this instruction is identical to (same
/// opcode and same operands as) the specified instruction.
bool isIdenticalTo(const MachineInstr *Other,
bool isIdenticalTo(const MachineInstr &Other,
MICheckType Check = CheckDefs) const;
/// Unlink 'this' from the containing basic block, and return it without
@ -1154,7 +1154,7 @@ public:
/// Copy implicit register operands from specified
/// instruction to this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
//
// Debugging support
@ -1297,7 +1297,7 @@ struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
LHS == getEmptyKey() || LHS == getTombstoneKey())
return LHS == RHS;
return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
}
};

2
include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -230,7 +230,7 @@ public:
/// Copy all the implicit operands from OtherMI onto this one.
const MachineInstrBuilder &
copyImplicitOps(const MachineInstr *OtherMI) const {
copyImplicitOps(const MachineInstr &OtherMI) const {
MI->copyImplicitOps(*MF, OtherMI);
return *this;
}

2
lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
View File

@ -40,7 +40,7 @@ void DbgValueHistoryMap::startInstrRange(InlinedVariable Var,
assert(MI.isDebugValue() && "not a DBG_VALUE");
auto &Ranges = VarInstrRanges[Var];
if (!Ranges.empty() && Ranges.back().second == nullptr &&
Ranges.back().first->isIdenticalTo(&MI)) {
Ranges.back().first->isIdenticalTo(MI)) {
DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n"
<< "\t" << Ranges.back().first << "\t" << MI << "\n");
return;

8
lib/CodeGen/BranchFolding.cpp
View File

@ -357,7 +357,7 @@ static unsigned ComputeCommonTailLength(MachineBasicBlock *MBB1,
--I2;
}
// I1, I2==first (untested) non-DBGs preceding known match
if (!I1->isIdenticalTo(I2) ||
if (!I1->isIdenticalTo(*I2) ||
// FIXME: This check is dubious. It's used to get around a problem where
// people incorrectly expect inline asm directives to remain in the same
// relative order. This is untenable because normal compiler
@ -777,7 +777,7 @@ removeMMOsFromMemoryOperations(MachineBasicBlock::iterator MBBIStartPos,
assert(MBBICommon != MBBIECommon &&
"Reached BB end within common tail length!");
assert(MBBICommon->isIdenticalTo(&*MBBI) && "Expected matching MIIs!");
assert(MBBICommon->isIdenticalTo(*MBBI) && "Expected matching MIIs!");
if (MBBICommon->mayLoad() || MBBICommon->mayStore())
MBBICommon->setMemRefs(MBBICommon->mergeMemRefsWith(*MBBI));
@ -1275,7 +1275,7 @@ ReoptimizeBlock:
// DBG_VALUE at the beginning of MBB.
while (PrevBBIter != PrevBB.begin() && MBBIter != MBB->end()
&& PrevBBIter->isDebugValue() && MBBIter->isDebugValue()) {
if (!MBBIter->isIdenticalTo(PrevBBIter))
if (!MBBIter->isIdenticalTo(*PrevBBIter))
break;
MachineInstr *DuplicateDbg = MBBIter;
++MBBIter; -- PrevBBIter;
@ -1762,7 +1762,7 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) {
if (FIB == FIE)
break;
}
if (!TIB->isIdenticalTo(FIB, MachineInstr::CheckKillDead))
if (!TIB->isIdenticalTo(*FIB, MachineInstr::CheckKillDead))
break;
if (TII->isPredicated(*TIB))

4
lib/CodeGen/IfConversion.cpp
View File

@ -580,7 +580,7 @@ bool IfConverter::ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
if (FIB == FIE)
break;
}
if (!TIB->isIdenticalTo(FIB))
if (!TIB->isIdenticalTo(*FIB))
break;
++Dups1;
++TIB;
@ -624,7 +624,7 @@ bool IfConverter::ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
if (FIE == FIB)
break;
}
if (!TIE->isIdenticalTo(FIE))
if (!TIE->isIdenticalTo(*FIE))
break;
++Dups2;
--TIE;

24
lib/CodeGen/MachineInstr.cpp
View File

@ -948,23 +948,23 @@ bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
}
}
bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
MICheckType Check) const {
// If opcodes or number of operands are not the same then the two
// instructions are obviously not identical.
if (Other->getOpcode() != getOpcode() ||
Other->getNumOperands() != getNumOperands())
if (Other.getOpcode() != getOpcode() ||
Other.getNumOperands() != getNumOperands())
return false;
if (isBundle()) {
// Both instructions are bundles, compare MIs inside the bundle.
MachineBasicBlock::const_instr_iterator I1 = getIterator();
MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
MachineBasicBlock::const_instr_iterator I2 = Other->getIterator();
MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
MachineBasicBlock::const_instr_iterator E2 = Other.getParent()->instr_end();
while (++I1 != E1 && I1->isInsideBundle()) {
++I2;
if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(&*I2, Check))
if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(*I2, Check))
return false;
}
}
@ -972,7 +972,7 @@ bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
// Check operands to make sure they match.
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
const MachineOperand &OMO = Other->getOperand(i);
const MachineOperand &OMO = Other.getOperand(i);
if (!MO.isReg()) {
if (!MO.isIdenticalTo(OMO))
return false;
@ -1005,8 +1005,8 @@ bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
}
// If DebugLoc does not match then two dbg.values are not identical.
if (isDebugValue())
if (getDebugLoc() && Other->getDebugLoc() &&
getDebugLoc() != Other->getDebugLoc())
if (getDebugLoc() && Other.getDebugLoc() &&
getDebugLoc() != Other.getDebugLoc())
return false;
return true;
}
@ -1615,10 +1615,10 @@ bool MachineInstr::allDefsAreDead() const {
/// copyImplicitOps - Copy implicit register operands from specified
/// instruction to this instruction.
void MachineInstr::copyImplicitOps(MachineFunction &MF,
const MachineInstr *MI) {
for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
const MachineInstr &MI) {
for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
const MachineOperand &MO = MI.getOperand(i);
if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
addOperand(MF, MO);
}

2
lib/CodeGen/TargetInstrInfo.cpp
View File

@ -383,7 +383,7 @@ bool
TargetInstrInfo::produceSameValue(const MachineInstr *MI0,
const MachineInstr *MI1,
const MachineRegisterInfo *MRI) const {
return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
return MI0->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs);
}
MachineInstr *TargetInstrInfo::duplicate(MachineInstr *Orig,

2
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -1531,7 +1531,7 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
return true;
}
return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
return MI0->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs);
}
/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to

2
lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -1027,7 +1027,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
for (unsigned i = 0, e = Regs.size(); i < e; ++i)
MIB.addReg(Regs[i], getDefRegState(true));
if (DeleteRet && MI != MBB.end()) {
MIB.copyImplicitOps(&*MI);
MIB.copyImplicitOps(*MI);
MI->eraseFromParent();
}
MI = MIB;

6
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -1818,7 +1818,7 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");
PrevMI->setDesc(TII->get(NewOpc));
MO.setReg(ARM::PC);
PrevMI->copyImplicitOps(*MBB.getParent(), &*MBBI);
PrevMI->copyImplicitOps(*MBB.getParent(), *MBBI);
MBB.erase(MBBI);
return true;
}
@ -1840,8 +1840,8 @@ bool ARMLoadStoreOpt::CombineMovBx(MachineBasicBlock &MBB) {
for (auto Use : Prev->uses())
if (Use.isKill()) {
AddDefaultPred(BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX))
.addReg(Use.getReg(), RegState::Kill))
.copyImplicitOps(&*MBBI);
.addReg(Use.getReg(), RegState::Kill))
.copyImplicitOps(*MBBI);
MBB.erase(MBBI);
MBB.erase(Prev);
return true;

2
lib/Target/ARM/Thumb1FrameLowering.cpp
View File

@ -637,7 +637,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
Reg = ARM::PC;
(*MIB).setDesc(TII.get(ARM::tPOP_RET));
if (MI != MBB.end())
MIB.copyImplicitOps(&*MI);
MIB.copyImplicitOps(*MI);
MI = MBB.erase(MI);
} else
// LR may only be popped into PC, as part of return sequence.

4
lib/Target/Hexagon/HexagonFrameLowering.cpp
View File

@ -572,7 +572,7 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
unsigned NewOpc = Hexagon::L4_return;
MachineInstr *NewI = BuildMI(MBB, RetI, DL, HII.get(NewOpc));
// Transfer the function live-out registers.
NewI->copyImplicitOps(MF, RetI);
NewI->copyImplicitOps(MF, *RetI);
MBB.erase(RetI);
}
@ -983,7 +983,7 @@ bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
DeallocCall = BuildMI(MBB, It, DL, HII.get(ROpc))
.addExternalSymbol(RestoreFn);
// Transfer the function live-out registers.
DeallocCall->copyImplicitOps(MF, It);
DeallocCall->copyImplicitOps(MF, *It);
}
addCalleeSaveRegistersAsImpOperand(DeallocCall, MaxR, true);
return true;

6
lib/Target/PowerPC/PPCEarlyReturn.cpp
View File

@ -84,7 +84,7 @@ protected:
// This is an unconditional branch to the return. Replace the
// branch with a blr.
BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
.copyImplicitOps(I);
.copyImplicitOps(*I);
MachineBasicBlock::iterator K = J--;
K->eraseFromParent();
BlockChanged = true;
@ -98,7 +98,7 @@ protected:
BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
.addImm(J->getOperand(0).getImm())
.addReg(J->getOperand(1).getReg())
.copyImplicitOps(I);
.copyImplicitOps(*I);
MachineBasicBlock::iterator K = J--;
K->eraseFromParent();
BlockChanged = true;
@ -113,7 +113,7 @@ protected:
**PI, J, J->getDebugLoc(),
TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
.addReg(J->getOperand(0).getReg())
.copyImplicitOps(I);
.copyImplicitOps(*I);
MachineBasicBlock::iterator K = J--;
K->eraseFromParent();
BlockChanged = true;

2
lib/Target/X86/X86ExpandPseudo.cpp
View File

@ -122,7 +122,7 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
}
MachineInstr *NewMI = std::prev(MBBI);
NewMI->copyImplicitOps(*MBBI->getParent()->getParent(), MBBI);
NewMI->copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
// Delete the pseudo instruction TCRETURN.
MBB.erase(MBBI);