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[Thumb] Fix infinite loop in ABS expansion (PR41160)
Don't expand ISD::ABS node if its legal. llvm-svn: 356661
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@ -10391,9 +10391,12 @@ static SDValue PerformABSCombine(SDNode *N,
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SelectionDAG &DAG = DCI.DAG;
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (!TLI.expandABS(N, res, DAG))
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if (TLI.isOperationLegal(N->getOpcode(), N->getValueType(0)))
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return SDValue();
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if (!TLI.expandABS(N, res, DAG))
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return SDValue();
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return res;
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}
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20
test/CodeGen/Thumb/iabs-vector.ll
Normal file
20
test/CodeGen/Thumb/iabs-vector.ll
Normal file
@ -0,0 +1,20 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7--- | FileCheck %s
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define void @PR41160(<8 x i32>* %p) nounwind {
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; CHECK-LABEL: PR41160:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.8 {d16, d17}, [r0]
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; CHECK-NEXT: vabs.s32 q8, q8
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; CHECK-NEXT: vst1.8 {d16, d17}, [r0]!
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; CHECK-NEXT: vld1.8 {d16, d17}, [r0]
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; CHECK-NEXT: vabs.s32 q8, q8
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; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
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; CHECK-NEXT: bx lr
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%tmp1 = load <8 x i32>, <8 x i32>* %p, align 1
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%tmp2 = icmp slt <8 x i32> %tmp1, zeroinitializer
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%tmp3 = sub nsw <8 x i32> zeroinitializer, %tmp1
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%tmp4 = select <8 x i1> %tmp2, <8 x i32> %tmp3, <8 x i32> %tmp1
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store <8 x i32> %tmp4, <8 x i32>* %p, align 1
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ret void
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}
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