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[lanai] Add areMemAccessesTriviallyDisjoint, getMemOpBaseRegImmOfs and getMemOpBaseRegImmOfsWidth.
Summary: Add getMemOpBaseRegImmOfsWidth to enable determining independence during MiSched. Reviewers: eliben, majnemer Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18903 llvm-svn: 266338
This commit is contained in:
Jacques Pienaar
parent
c0b7282ebc
commit
77c93881e7
@ -23,10 +23,11 @@
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "LanaiGenInstrInfo.inc"
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namespace llvm {
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LanaiInstrInfo::LanaiInstrInfo()
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: LanaiGenInstrInfo(Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
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RegisterInfo() {}
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@ -84,6 +85,38 @@ void LanaiInstrInfo::loadRegFromStackSlot(
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.addImm(LPAC::ADD);
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}
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bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
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MachineInstr *MIb,
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AliasAnalysis *AA) const {
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assert(MIa && MIa->mayLoadOrStore() && "MIa must be a load or store.");
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assert(MIb && MIb->mayLoadOrStore() && "MIb must be a load or store.");
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if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
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MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
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return false;
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// Retrieve the base register, offset from the base register and width. Width
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// is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
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// base registers are identical, and the offset of a lower memory access +
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// the width doesn't overlap the offset of a higher memory access,
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// then the memory accesses are different.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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unsigned BaseRegA = 0, BaseRegB = 0;
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int64_t OffsetA = 0, OffsetB = 0;
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unsigned int WidthA = 0, WidthB = 0;
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if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) &&
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getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) {
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if (BaseRegA == BaseRegB) {
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int LowOffset = std::min(OffsetA, OffsetB);
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int HighOffset = std::max(OffsetA, OffsetB);
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int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
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if (LowOffset + LowWidth <= HighOffset)
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return true;
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}
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}
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return false;
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}
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bool LanaiInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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return false;
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}
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@ -321,4 +354,61 @@ unsigned LanaiInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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}
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return 0;
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}
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} // namespace llvm
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bool LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(
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MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const {
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// Handle only loads/stores with base register followed by immediate offset
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// and with add as ALU op.
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if (LdSt->getNumOperands() != 4)
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return false;
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if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm() ||
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!(LdSt->getOperand(3).isImm() &&
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LdSt->getOperand(3).getImm() == LPAC::ADD))
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return false;
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switch (LdSt->getOpcode()) {
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default:
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return false;
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case Lanai::LDW_RI:
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case Lanai::LDW_RR:
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case Lanai::SW_RR:
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case Lanai::SW_RI:
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Width = 4;
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break;
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case Lanai::LDHs_RI:
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case Lanai::LDHz_RI:
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case Lanai::STH_RI:
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Width = 2;
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break;
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case Lanai::LDBs_RI:
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case Lanai::LDBz_RI:
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case Lanai::STB_RI:
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Width = 1;
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break;
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}
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BaseReg = LdSt->getOperand(1).getReg();
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Offset = LdSt->getOperand(2).getImm();
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return true;
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}
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bool LanaiInstrInfo::getMemOpBaseRegImmOfs(
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MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset,
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const TargetRegisterInfo *TRI) const {
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switch (LdSt->getOpcode()) {
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default:
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return false;
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case Lanai::LDW_RI:
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case Lanai::LDW_RR:
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case Lanai::SW_RR:
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case Lanai::SW_RI:
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case Lanai::LDHs_RI:
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case Lanai::LDHz_RI:
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case Lanai::STH_RI:
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case Lanai::LDBs_RI:
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case Lanai::LDBz_RI:
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unsigned Width;
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return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI);
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}
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}
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@ -35,6 +35,9 @@ public:
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return RegisterInfo;
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}
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bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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AliasAnalysis *AA) const override;
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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@ -64,6 +67,14 @@ public:
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
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int64_t &Offset,
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const TargetRegisterInfo *TRI) const override;
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bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
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int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock,
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MachineBasicBlock *&FalseBlock,
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SmallVectorImpl<MachineOperand> &Condition,
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55
test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll
Normal file
55
test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll
Normal file
@ -0,0 +1,55 @@
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; RUN: llc %s -mtriple=lanai-unknown-unknown -debug-only=misched -o /dev/null 2>&1 | FileCheck %s
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; Make sure there are no control dependencies between memory operations that
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; are trivially disjoint.
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; Function Attrs: norecurse nounwind uwtable
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define i32 @foo(i8* inreg nocapture %x) {
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entry:
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%0 = bitcast i8* %x to i32*
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store i32 1, i32* %0, align 4
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%arrayidx1 = getelementptr inbounds i8, i8* %x, i32 4
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%1 = bitcast i8* %arrayidx1 to i32*
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store i32 2, i32* %1, align 4
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%arrayidx2 = getelementptr inbounds i8, i8* %x, i32 12
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%2 = bitcast i8* %arrayidx2 to i32*
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%3 = load i32, i32* %2, align 4
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%arrayidx3 = getelementptr inbounds i8, i8* %x, i32 10
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%4 = bitcast i8* %arrayidx3 to i16*
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store i16 3, i16* %4, align 2
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%5 = bitcast i8* %arrayidx2 to i16*
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store i16 4, i16* %5, align 2
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%arrayidx5 = getelementptr inbounds i8, i8* %x, i32 14
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store i8 5, i8* %arrayidx5, align 1
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%arrayidx6 = getelementptr inbounds i8, i8* %x, i32 15
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store i8 6, i8* %arrayidx6, align 1
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%arrayidx7 = getelementptr inbounds i8, i8* %x, i32 16
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store i8 7, i8* %arrayidx7, align 1
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ret i32 %3
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}
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; CHECK-LABEL: foo
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; CHECK-LABEL: SU({{.*}}): SW_RI{{.*}}, 0,
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; CHECK: # preds left : 2
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; CHECK: # succs left : 0
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; CHECK-LABEL: SU({{.*}}): SW_RI{{.*}}, 4,
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; CHECK: # preds left : 2
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; CHECK: # succs left : 0
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; CHECK-LABEL: SU({{.*}}): %vreg{{.*}}<def> = LDW_RI{{.*}}, 12,
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; CHECK: # preds left : 1
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; CHECK: # succs left : 4
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; CHECK-LABEL: SU({{.*}}): STH_RI{{.*}}, 10,
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; CHECK: # preds left : 2
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; CHECK: # succs left : 0
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; CHECK-LABEL: SU({{.*}}): STH_RI{{.*}}, 12,
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; CHECK: # preds left : 3
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; CHECK: # succs left : 0
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; CHECK-LABEL: SU({{.*}}): STB_RI{{.*}}, 14,
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; CHECK: # preds left : 3
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; CHECK: # succs left : 0
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; CHECK-LABEL: SU({{.*}}): STB_RI{{.*}}, 15,
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; CHECK: # preds left : 3
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; CHECK: # succs left : 0
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; CHECK-LABEL: SU({{.*}}): STB_RI{{.*}}, 16,
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; CHECK: # preds left : 2
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; CHECK: # succs left : 0
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